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Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macr
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips |
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Date: |
Fri, 15 Jun 2018 11:44:38 +0100 |
On 11 June 2018 at 23:03, Alistair Francis <address@hidden> wrote:
> On Mon, Jun 11, 2018 at 10:18 AM, Cédric Le Goater <address@hidden> wrote:
>> On 06/11/2018 07:15 PM, Cédric Le Goater wrote:
>>> On Macronix chips, two bytes can written to the WRSR. First byte will
>>> configure the status register and the second the configuration
>>> register. It is important to save the configuration value as it
>>> contains the dummy cycle setting when using dual or quad IO mode.
>>>
>>> Signed-off-by: Cédric Le Goater <address@hidden>
>
> Acked-by: Alistair Francis <address@hidden>
Applied to target-arm.next, thanks.
-- PMM