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Re: [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount wit
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC |
Date: |
Tue, 29 May 2018 16:47:38 -0700 |
On Tue, May 22, 2018 at 5:15 PM, Michael Clark <address@hidden> wrote:
> The mode variable only uses the lower 4-bits (M,H,S,U) so
> replace the GCC specific __builtin_popcount with ctpop8.
>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/riscv/sifive_plic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index b267ff88902d..dc6f4924e282 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -383,7 +383,7 @@ static void parse_hart_config(SiFivePLICState *plic)
> p = plic->hart_config;
> while ((c = *p++)) {
> if (c == ',') {
> - addrid += __builtin_popcount(modes);
> + addrid += ctpop8(modes);
> modes = 0;
> hartid++;
> } else {
> @@ -397,7 +397,7 @@ static void parse_hart_config(SiFivePLICState *plic)
> }
> }
> if (modes) {
> - addrid += __builtin_popcount(modes);
> + addrid += ctpop8(modes);
> }
> hartid++;
>
> --
> 2.7.0
>
>
- Re: [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM, (continued)
- [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22