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[Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup ind
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation |
Date: |
Tue, 29 May 2018 12:50:10 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Fixup the indentation of cpu_mmu_index in preparation for
future edits.
No functional changes.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.h | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e38580cd7f..c77ca2d8f9 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -360,13 +360,15 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
{
- /* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM))
- return MMU_NOMMU_IDX;
-
- if (env->sregs[SR_MSR] & MSR_UM)
- return MMU_USER_IDX;
- return MMU_KERNEL_IDX;
+ /* Are we in nommu mode?. */
+ if (!(env->sregs[SR_MSR] & MSR_VM)) {
+ return MMU_NOMMU_IDX;
+ }
+
+ if (env->sregs[SR_MSR] & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
}
int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
--
2.14.1
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, (continued)
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 30/38] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 29/38] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 32/38] target-microblaze: mmu: Cleanup debug log messages, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 34/38] target-microblaze: Remove argument b in eval_cc(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 35/38] target-microblaze: Convert env_btarget to i64, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 38/38] target-microblaze: Consolidate MMU enabled checks, Edgar E. Iglesias, 2018/05/29
- Re: [Qemu-devel] [PULL v1 00/38] Xilinx queue, Peter Maydell, 2018/05/29