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[Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR check
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks |
Date: |
Tue, 29 May 2018 12:49:41 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
We already have a CPU property to control if a core has
an MMU or not. Remove USE_MMU PVR checks in favor of
looking at the property.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/helper.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 387d4aca5a..a9f4ca93e3 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -54,21 +54,11 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int size, int rw,
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
unsigned int hit;
- unsigned int mmu_available;
int r = 1;
int prot;
- mmu_available = 0;
- if (cpu->cfg.use_mmu) {
- mmu_available = 1;
- if ((cpu->cfg.pvr == C_PVR_FULL) &&
- (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
- mmu_available = 0;
- }
- }
-
/* Translate if the MMU is available and enabled. */
- if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
+ if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM)) {
uint32_t vaddr, paddr;
struct microblaze_mmu_lookup lu;
--
2.14.1
- [Qemu-devel] [PULL v1 00/38] Xilinx queue, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 01/38] target-microblaze: dec_load: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 03/38] target-microblaze: compute_ldst_addr: Use bool instead of int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 04/38] target-microblaze: Fallback to our latest CPU version, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 02/38] target-microblaze: dec_store: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 05/38] target-microblaze: Correct special register array sizes, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 06/38] target-microblaze: Correct the PVR array size, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 10/38] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 11/38] target-microblaze: Make compute_ldst_addr always use a temp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 13/38] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 17/38] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/29