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Re: [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config |
Date: |
Wed, 23 May 2018 09:40:14 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/22/2018 09:15 PM, Michael Clark wrote:
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> hw/riscv/virt.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index ad03113e0f72..321fa6e8122a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> + g_free(plic_hart_config);
> }
>
> static void riscv_virt_board_machine_init(MachineClass *mc)
>
- Re: [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM, (continued)
- [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22
- Re: [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads, Michael Clark, 2018/05/22