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[Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pend
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending |
Date: |
Wed, 23 May 2018 12:14:51 +1200 |
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
target/riscv/helper.c | 34 ++++++++++++----------------------
1 file changed, 12 insertions(+), 22 deletions(-)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 3b57e1360549..47d116e9c13f 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -35,28 +35,18 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
}
#ifndef CONFIG_USER_ONLY
-/*
- * Return RISC-V IRQ number if an interrupt should be taken, else -1.
- * Used in cpu-exec.c
- *
- * Adapted from Spike's processor_t::take_interrupt()
- */
-static int riscv_cpu_hw_interrupts_pending(CPURISCVState *env)
+static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
- target_ulong pending_interrupts = atomic_read(&env->mip) & env->mie;
-
- target_ulong mie = get_field(env->mstatus, MSTATUS_MIE);
- target_ulong m_enabled = env->priv < PRV_M || (env->priv == PRV_M && mie);
- target_ulong enabled_interrupts = pending_interrupts &
- ~env->mideleg & -m_enabled;
-
- target_ulong sie = get_field(env->mstatus, MSTATUS_SIE);
- target_ulong s_enabled = env->priv < PRV_S || (env->priv == PRV_S && sie);
- enabled_interrupts |= pending_interrupts & env->mideleg &
- -s_enabled;
-
- if (enabled_interrupts) {
- return ctz64(enabled_interrupts); /* since non-zero */
+ target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
+ target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
+ target_ulong pending = atomic_read(&env->mip) & env->mie;
+ target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
+ target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong irqs = (pending & ~env->mideleg & -mie) |
+ (pending & env->mideleg & -sie);
+
+ if (irqs) {
+ return ctz64(irqs); /* since non-zero */
} else {
return EXCP_NONE; /* indicates no pending interrupt */
}
@@ -69,7 +59,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- int interruptno = riscv_cpu_hw_interrupts_pending(env);
+ int interruptno = riscv_cpu_local_irq_pending(env);
if (interruptno >= 0) {
cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
riscv_cpu_do_interrupt(cs);
--
2.7.0
- [Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending,
Michael Clark <=
- [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/05/22