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[Qemu-devel] [PULL 28/32] target/arm: Implement SVE floating-point trig
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 28/32] target/arm: Implement SVE floating-point trig select coefficient |
Date: |
Fri, 18 May 2018 18:20:05 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper-sve.h | 4 ++++
target/arm/sve_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 21 +++++++++++++++++++
target/arm/sve.decode | 4 ++++
4 files changed, 72 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index e2925ff8ec..4f1bd5a62f 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -389,6 +389,10 @@ DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void,
ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 6ffb126821..85a0639e3a 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -23,6 +23,7 @@
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
+#include "fpu/softfloat.h"
/* Note that vector data is stored in host-endian 64-bit chunks,
@@ -1192,3 +1193,45 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_t
desc)
d[i] = coeff[idx] | (exp << 52);
}
}
+
+void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 2;
+ uint16_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ uint16_t nn = n[i];
+ uint16_t mm = m[i];
+ if (mm & 1) {
+ nn = float16_one;
+ }
+ d[i] = nn ^ (mm & 2) << 14;
+ }
+}
+
+void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 4;
+ uint32_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ uint32_t nn = n[i];
+ uint32_t mm = m[i];
+ if (mm & 1) {
+ nn = float32_one;
+ }
+ d[i] = nn ^ (mm & 2) << 30;
+ }
+}
+
+void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ uint64_t nn = n[i];
+ uint64_t mm = m[i];
+ if (mm & 1) {
+ nn = float64_one;
+ }
+ d[i] = nn ^ (mm & 2) << 62;
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 54d774b5e0..ea8d2c4112 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -953,6 +953,27 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a,
uint32_t insn)
return true;
}
+static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ static gen_helper_gvec_3 * const fns[4] = {
+ NULL,
+ gen_helper_sve_ftssel_h,
+ gen_helper_sve_ftssel_s,
+ gen_helper_sve_ftssel_d,
+ };
+ if (a->esz == 0) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, fns[a->esz]);
+ }
+ return true;
+}
+
/*
*** SVE Predicate Logical Operations Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index cd53b95831..224dfdd1e9 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -295,6 +295,10 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... .....
@rd_rn_msz_rm
# Note esz != 0
FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
+# SVE floating-point trig select coefficient
+# Note esz != 0
+FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
--
2.17.0
- [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, (continued)
- [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 23/32] target/arm: Implement SVE Index Generation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 17/32] target/arm: Implement SVE bitwise shift by immediate (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 21/32] target/arm: Implement SVE Integer Multiply-Add Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 30/32] target/arm: Implement SVE Bitwise Immediate Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 29/32] target/arm: Implement SVE Element Count Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 31/32] target/arm: Implement SVE Integer Wide Immediate - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 25/32] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 27/32] target/arm: Implement SVE floating-point exponential accelerator, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 28/32] target/arm: Implement SVE floating-point trig select coefficient,
Peter Maydell <=
- [Qemu-devel] [PULL 32/32] target/arm: Implement SVE Permute - Extract Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 26/32] target/arm: Implement SVE Compute Vector Address Group, Peter Maydell, 2018/05/18
- Re: [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/05/18