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[Qemu-devel] [PATCH v3 00/38] target-microblaze: Add support for Extende
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v3 00/38] target-microblaze: Add support for Extended Addressing |
Date: |
Wed, 16 May 2018 20:51:08 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
This series adds support for Extended Addressing to our MicroBlaze
models. It adds both the non-MMU load/store EA and the extended MMU
addressing.
There are several ways to implement this but since there are further
64-bit extensions in the pipe, I've chosen to convert the cpu_SR
special regs to 64-bit. Both non-EA and EA enabled cores run out of
the same build with TARGET_LONG_BITS=64.
Comments?
The following lacks review:
$ grep -L Reviewed v3/patches/*
v3/patches/0000-cover-letter.patch
v3/patches/0028-target-microblaze-dec_msr-Plug-a-temp-leak.patch
v3/patches/0029-target-microblaze-Add-support-for-extended-access-to.patch
v3/patches/0035-target-microblaze-Convert-env_btarget-to-i64.patch
v3/patches/0036-target-microblaze-Use-tcg_gen_movcond-in-eval_cond_j.patch
v3/patches/0037-target-microblaze-cpu_mmu_index-Fixup-indentation.patch
v3/patches/0038-target-microblaze-Consolidate-MMU-enabled-checks.patch
Thanks & Best regards,
Edgar
ChangeLog:
v2 -> v3:
* Add patch to consolidate MMU enabled checks
* Remove patch to convert env_btaken to 64bits
* Add patch to plug tcg_const leakage
* Fix TLBLO access patch to avoid leaking tcg consts
v1 -> v2:
* Add patch to simplify address computation using tcg_gen_addi_i32()
* Add patches to cleanup eval_cond_jmp using tcg_gen_movcond_i32()
* Add patch to cleanup microblaze MMU logs
* Correct trap_userspace() usage when adding Extended Addressing
* Correct name for special register sr13 to redr
Edgar E. Iglesias (38):
target-microblaze: dec_load: Use bool instead of unsigned int
target-microblaze: dec_store: Use bool instead of unsigned int
target-microblaze: compute_ldst_addr: Use bool instead of int
target-microblaze: Fallback to our latest CPU version
target-microblaze: Correct special register array sizes
target-microblaze: Correct the PVR array size
target-microblaze: Tighten up TCGv_i32 vs TCGv type usage
target-microblaze: Remove USE_MMU PVR checks
target-microblaze: Conditionalize setting of PVR11_USE_MMU
target-microblaze: Bypass MMU with MMU_NOMMU_IDX
target-microblaze: Make compute_ldst_addr always use a temp
target-microblaze: Remove pointer indirection for ld/st addresses
target-microblaze: Use TCGv for load/store addresses
target-microblaze: Name special registers we support
target-microblaze: Break out trap_userspace()
target-microblaze: Break out trap_illegal()
target-microblaze: dec_msr: Use bool and extract32
target-microblaze: dec_msr: Reuse more code when reg-decoding
target-microblaze: dec_msr: Fix MTS to FSR
target-microblaze: Make special registers 64-bit
target-microblaze: Setup for 64bit addressing
target-microblaze: Add Extended Addressing
target-microblaze: Implement MFSE EAR
target-microblaze: mmu: Add R_TBLX_MISS macros
target-microblaze: mmu: Remove unused register state
target-microblaze: mmu: Prepare for 64-bit addresses
target-microblaze: mmu: Add a configurable output address mask
target-microblaze: dec_msr: Plug a temp leak
target-microblaze: Add support for extended access to TLBLO
target-microblaze: Allow address sizes between 32 and 64 bits
target-microblaze: Simplify address computation using
tcg_gen_addi_i32()
target-microblaze: mmu: Cleanup debug log messages
target-microblaze: Use table based condition-codes conversion
target-microblaze: Remove argument b in eval_cc()
target-microblaze: Convert env_btarget to i64
target-microblaze: Use tcg_gen_movcond in eval_cond_jmp
target-microblaze: cpu_mmu_index: Fixup indentation
target-microblaze: Consolidate MMU enabled checks
configure | 1 +
linux-user/microblaze/cpu_loop.c | 4 +-
target/microblaze/cpu.c | 30 +-
target/microblaze/cpu.h | 34 +-
target/microblaze/helper.c | 32 +-
target/microblaze/helper.h | 8 +-
target/microblaze/mmu.c | 81 ++--
target/microblaze/mmu.h | 17 +-
target/microblaze/op_helper.c | 30 +-
target/microblaze/translate.c | 930 +++++++++++++++++++--------------------
10 files changed, 598 insertions(+), 569 deletions(-)
--
2.14.1
- [Qemu-devel] [PATCH v3 00/38] target-microblaze: Add support for Extended Addressing,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v3 02/38] target-microblaze: dec_store: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 03/38] target-microblaze: compute_ldst_addr: Use bool instead of int, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 01/38] target-microblaze: dec_load: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 04/38] target-microblaze: Fallback to our latest CPU version, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 05/38] target-microblaze: Correct special register array sizes, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 08/38] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 06/38] target-microblaze: Correct the PVR array size, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/16