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[Qemu-devel] [PATCH v6 25/28] fpu/softfloat: Pass FloatClass to pickNaNM
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v6 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd |
Date: |
Tue, 15 May 2018 15:25:37 -0700 |
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaNMulAdd into a single function whose body is ifdef-selected.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
fpu/softfloat-specialize.h | 70 +++++++++++++++-----------------------
fpu/softfloat.c | 5 +--
2 files changed, 28 insertions(+), 47 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 2695183188..0399dfe011 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
| information.
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
*----------------------------------------------------------------------------*/
-#if defined(TARGET_ARM)
-static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag
bIsSNaN,
- flag cIsQNaN, flag cIsSNaN, flag infzero,
- float_status *status)
+static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
+ bool infzero, float_status *status)
{
+#if defined(TARGET_ARM)
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
* the default NaN
*/
- if (infzero && cIsQNaN) {
+ if (infzero && is_qnan(c_cls)) {
float_raise(float_flag_invalid, status);
return 3;
}
@@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
*/
- if (cIsSNaN) {
+ if (is_snan(c_cls)) {
return 2;
- } else if (aIsSNaN) {
+ } else if (is_snan(a_cls)) {
return 0;
- } else if (bIsSNaN) {
+ } else if (is_snan(b_cls)) {
return 1;
- } else if (cIsQNaN) {
+ } else if (is_qnan(c_cls)) {
return 2;
- } else if (aIsQNaN) {
+ } else if (is_qnan(a_cls)) {
return 0;
} else {
return 1;
}
-}
#elif defined(TARGET_MIPS)
-static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag
bIsSNaN,
- flag cIsQNaN, flag cIsSNaN, flag infzero,
- float_status *status)
-{
/* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
* the default NaN
*/
@@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
if (snan_bit_is_one(status)) {
/* Prefer sNaN over qNaN, in the a, b, c order. */
- if (aIsSNaN) {
+ if (is_snan(a_cls)) {
return 0;
- } else if (bIsSNaN) {
+ } else if (is_snan(b_cls)) {
return 1;
- } else if (cIsSNaN) {
+ } else if (is_snan(c_cls)) {
return 2;
- } else if (aIsQNaN) {
+ } else if (is_qnan(a_cls)) {
return 0;
- } else if (bIsQNaN) {
+ } else if (is_qnan(b_cls)) {
return 1;
} else {
return 2;
}
} else {
/* Prefer sNaN over qNaN, in the c, a, b order. */
- if (cIsSNaN) {
+ if (is_snan(c_cls)) {
return 2;
- } else if (aIsSNaN) {
+ } else if (is_snan(a_cls)) {
return 0;
- } else if (bIsSNaN) {
+ } else if (is_snan(b_cls)) {
return 1;
- } else if (cIsQNaN) {
+ } else if (is_qnan(c_cls)) {
return 2;
- } else if (aIsQNaN) {
+ } else if (is_qnan(a_cls)) {
return 0;
} else {
return 1;
}
}
-}
#elif defined(TARGET_PPC)
-static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag
bIsSNaN,
- flag cIsQNaN, flag cIsSNaN, flag infzero,
- float_status *status)
-{
/* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
* to return an input NaN if we have one (ie c) rather than generating
* a default NaN
@@ -686,31 +675,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
*/
- if (aIsSNaN || aIsQNaN) {
+ if (is_nan(a_cls)) {
return 0;
- } else if (cIsSNaN || cIsQNaN) {
+ } else if (is_nan(c_cls)) {
return 2;
} else {
return 1;
}
-}
#else
-/* A default implementation: prefer a to b to c.
- * This is unlikely to actually match any real implementation.
- */
-static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag
bIsSNaN,
- flag cIsQNaN, flag cIsSNaN, flag infzero,
- float_status *status)
-{
- if (aIsSNaN || aIsQNaN) {
+ /* A default implementation: prefer a to b to c.
+ * This is unlikely to actually match any real implementation.
+ */
+ if (is_nan(a_cls)) {
return 0;
- } else if (bIsSNaN || bIsQNaN) {
+ } else if (is_nan(b_cls)) {
return 1;
} else {
return 2;
}
-}
#endif
+}
/*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 55954385ff..8e97602ace 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -601,10 +601,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts
b, FloatParts c,
s->float_exception_flags |= float_flag_invalid;
}
- which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls),
- is_qnan(b.cls), is_snan(b.cls),
- is_qnan(c.cls), is_snan(c.cls),
- inf_zero, s);
+ which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s);
if (s->default_nan_mode) {
/* Note that this check is after pickNaNMulAdd so that function
--
2.17.0
- [Qemu-devel] [PATCH v6 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN, (continued)
- [Qemu-devel] [PATCH v6 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 12/28] fpu/softfloat: re-factor float to float conversions, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 15/28] target/hppa: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 17/28] target/mips: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 19/28] target/s390x: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 18/28] target/riscv: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 21/28] fpu/softfloat: Remove floatX_maybe_silence_nan, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 23/28] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 22/28] fpu/softfloat: Specialize on snan_bit_is_one, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd,
Richard Henderson <=
- [Qemu-devel] [PATCH v6 24/28] fpu/softfloat: Pass FloatClass to pickNaN, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 27/28] fpu/softfloat: Clean up parts_default_nan, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 26/28] fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan, Richard Henderson, 2018/05/15
- [Qemu-devel] [PATCH v6 28/28] fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan, Richard Henderson, 2018/05/15
- Re: [Qemu-devel] [PATCH v6 00/28] softfloat patch roundup, Alex Bennée, 2018/05/16