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[Qemu-devel] [PATCH v2 07/27] fpu/softfloat: Introduce parts_is_snan_fra
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 07/27] fpu/softfloat: Introduce parts_is_snan_frac |
Date: |
Fri, 11 May 2018 17:42:51 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
fpu/softfloat-specialize.h | 15 +++++++++++++++
fpu/softfloat.c | 12 ++----------
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4fc9ea4ac0..515cb12cfa 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -86,6 +86,21 @@ this code that are retained.
#define NO_SIGNALING_NANS 1
#endif
+/*----------------------------------------------------------------------------
+| For the deconstructed floating-point with fraction FRAC, return true
+| if the fraction represents a signalling NaN; otherwise false.
+*----------------------------------------------------------------------------*/
+
+static bool parts_is_snan_frac(uint64_t frac, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return false;
+#else
+ flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
+ return msb == status->snan_bit_is_one;
+#endif
+}
+
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index a56d3d975b..cb68f2eb20 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const
FloatFmt *parm,
part.cls = float_class_inf;
} else {
part.frac <<= parm->frac_shift;
-#ifdef NO_SIGNALING_NANS
- part.cls = float_class_qnan;
-#else
- int64_t msb = part.frac << 2;
- if ((msb < 0) == status->snan_bit_is_one) {
- part.cls = float_class_snan;
- } else {
- part.cls = float_class_qnan;
- }
-#endif
+ part.cls = (parts_is_snan_frac(part.frac, status)
+ ? float_class_snan : float_class_qnan);
}
} else if (part.exp == 0) {
if (likely(part.frac == 0)) {
--
2.17.0
- [Qemu-devel] [PATCH v2 02/27] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), (continued)
- [Qemu-devel] [PATCH v2 02/27] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 03/27] fpu/softfloat: Merge NO_SIGNALING_NANS definitions, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 05/27] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 06/27] fpu/softfloat: Canonicalize NaN fraction, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 04/27] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 07/27] fpu/softfloat: Introduce parts_is_snan_frac,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 08/27] fpu/softfloat: Replace float_class_dnan with parts_default_nan, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 09/27] fpu/softfloat: Replace float_class_msnan with parts_silence_nan, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 10/27] fpu/softfloat: re-factor float to float conversions, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 12/27] target/arm: Use floatX_silence_nan when we have already checked for SNaN, Richard Henderson, 2018/05/11
- [Qemu-devel] [PATCH v2 11/27] fpu/softfloat: support ARM Alternative half-precision, Richard Henderson, 2018/05/11