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[Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM E
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device |
Date: |
Fri, 11 May 2018 16:28:39 -0700 |
Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.
Signed-off-by: Alistair Francis <address@hidden>
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/sifive_u.c | 50 +++++++++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 9 ++++--
4 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index f9e742120c..9a1c42e8b2 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -2,3 +2,4 @@
CONFIG_SERIAL=y
CONFIG_VIRTIO=y
+CONFIG_CADENCE=y
diff --git a/default-configs/riscv64-softmmu.mak
b/default-configs/riscv64-softmmu.mak
index f9e742120c..9a1c42e8b2 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -2,3 +2,4 @@
CONFIG_SERIAL=y
CONFIG_VIRTIO=y
+CONFIG_CADENCE=y
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 540d53bf2f..fff36bd04d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -60,8 +60,11 @@ static const struct MemmapEntry {
[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
+#define GEM_REVISION 0x10070109
+
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
@@ -194,6 +197,27 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/address@hidden",
+ (long)memmap[SIFIVE_U_GEM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_GEM].base,
+ 0x0, memmap[SIFIVE_U_GEM].size);
+ qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+ qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
+ qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/address@hidden/address@hidden",
+ (long)memmap[SIFIVE_U_GEM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/address@hidden",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -296,6 +320,9 @@ static void riscv_sifive_u54_init(Object *obj)
memmap[SIFIVE_U_MROM].size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
+
+ object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
+ qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
}
static void riscv_sifive_u54_realize(DeviceState *dev, Error **errp)
@@ -303,6 +330,10 @@ static void riscv_sifive_u54_realize(DeviceState *dev,
Error **errp)
SiFiveU54State *s = RISCV_U54_SOC(dev);
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
+ qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
+ int i;
+ Error *err = NULL;
+ NICInfo *nd = &nd_table[0];
object_property_set_bool(OBJECT(&s->cpus), true, "realized",
&error_abort);
@@ -327,6 +358,25 @@ static void riscv_sifive_u54_realize(DeviceState *dev,
Error **errp)
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
memmap[SIFIVE_U_CLINT].size, smp_cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+
+ for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
+ plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
+ }
+
+ if (nd->used) {
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+ qdev_set_nic_properties(DEVICE(&s->gem), nd);
+ }
+ object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
+ plic_gpios[SIFIVE_U_GEM_IRQ]);
}
static void riscv_sifive_u_machine_init(MachineClass *mc)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 0f8bdd8fab..ee1a9e291f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,6 +19,8 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
+#include "hw/net/cadence_gem.h"
+
#define TYPE_RISCV_U54_SOC "riscv.sifive.u54"
#define RISCV_U54_SOC(obj) \
OBJECT_CHECK(SiFiveU54State, (obj), TYPE_RISCV_U54_SOC)
@@ -30,6 +32,7 @@ typedef struct SiFiveU54State {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ CadenceGEMState gem;
} SiFiveU54State;
typedef struct SiFiveUState {
@@ -49,12 +52,14 @@ enum {
SIFIVE_U_PLIC,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
- SIFIVE_U_DRAM
+ SIFIVE_U_DRAM,
+ SIFIVE_U_GEM
};
enum {
SIFIVE_U_UART0_IRQ = 3,
- SIFIVE_U_UART1_IRQ = 4
+ SIFIVE_U_UART1_IRQ = 4,
+ SIFIVE_U_GEM_IRQ = 0x35
};
enum {
--
2.17.0
- [Qemu-devel] [PATCH v2 0/7] RISC-V: SoCify SiFive boards and connect GEM, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 1/7] hw/riscv/sifive_u: Create a U54 SoC object, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 2/7] hw/riscv/sifive_e: Create a E31 SoC object, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/05/11
- [Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device,
Alistair Francis <=