[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v8 3/8] i386: Add new property to control cache
From: |
Moger, Babu |
Subject: |
Re: [Qemu-devel] [PATCH v8 3/8] i386: Add new property to control cache info |
Date: |
Fri, 11 May 2018 20:21:50 +0000 |
> -----Original Message-----
> From: Eduardo Habkost [mailto:address@hidden
> Sent: Friday, May 11, 2018 2:22 PM
> To: Moger, Babu <address@hidden>
> Cc: address@hidden; address@hidden; address@hidden;
> address@hidden; address@hidden; address@hidden;
> address@hidden; address@hidden; address@hidden
> Subject: Re: [PATCH v8 3/8] i386: Add new property to control cache info
>
> On Thu, May 10, 2018 at 03:41:43PM -0500, Babu Moger wrote:
> > The property legacy-cache will be used to control the cache information.
> > If user passes "-cpu legacy-cache" then older information will
> > be displayed even if the hardware supports new information. Otherwise
> > use the statically loaded cache definitions if available.
> >
> > Signed-off-by: Babu Moger <address@hidden>
> > Tested-by: Geoffrey McRae <address@hidden>
> > ---
> > include/hw/i386/pc.h | 8 ++++
> > target/i386/cpu.c | 97 ++++++++++++++++++++++++++++++++-----------
> -
> > target/i386/cpu.h | 5 +++
> > 3 files changed, 84 insertions(+), 26 deletions(-)
> >
> > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > index 2e834e6ded..df15deefca 100644
> > --- a/include/hw/i386/pc.h
> > +++ b/include/hw/i386/pc.h
> > @@ -304,6 +304,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
> > int e820_get_num_entries(void);
> > bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
> >
> > +#define PC_COMPAT_2_12 \
> > + HW_COMPAT_2_12 \
> > + {\
> > + .driver = TYPE_X86_CPU,\
> > + .property = "legacy-cache",\
> > + .value = "on",\
> > + },
>
> This isn't enough if the pc-*-2.12 machine-type isn't using the
> macro.
>
> Before we do this, we need a commit similar to commit
> df47ce8af4a5, but adding pc-*-2.13 machine-types.
Ok. Sure. I think I got it. Will add pc-*-2.13 machine-types in v9 series.
>
> The rest of the patch looks good to me, but I will suggest a
> clean up (that can be submitted a separate patch later, or
> included in v9) in a separate reply.
Either way is works for me. If it is simple enough we can add here.
>
> --
> Eduardo
- [Qemu-devel] [PATCH v8 4/8] i386: Initialize cache information for EPYC family processors, (continued)
- [Qemu-devel] [PATCH v8 4/8] i386: Initialize cache information for EPYC family processors, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 7/8] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 5/8] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 6/8] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 1/8] i386: Helpers to encode cache information consistently, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 3/8] i386: Add new property to control cache info, Babu Moger, 2018/05/10
[Qemu-devel] [PATCH v8 8/8] i386: Remove generic SMT thread check, Babu Moger, 2018/05/10