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[Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16 |
Date: |
Thu, 10 May 2018 18:45:16 +0100 |
From: Richard Henderson <address@hidden>
While we have some of the scalar paths for *CVF for fp16,
we failed to decode the fp16 version of these instructions.
Cc: address@hidden
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 33 ++++++++++++++++++++-------------
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fa60cf908f..f4e2afa72c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7405,13 +7405,26 @@ static void handle_simd_shift_intfp_conv(DisasContext
*s, bool is_scalar,
int immh, int immb, int opcode,
int rn, int rd)
{
- bool is_double = extract32(immh, 3, 1);
- int size = is_double ? MO_64 : MO_32;
- int elements;
+ int size, elements, fracbits;
int immhb = immh << 3 | immb;
- int fracbits = (is_double ? 128 : 64) - immhb;
- if (!extract32(immh, 2, 2)) {
+ if (immh & 8) {
+ size = MO_64;
+ if (!is_scalar && !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ } else if (immh & 4) {
+ size = MO_32;
+ } else if (immh & 2) {
+ size = MO_16;
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
+ }
+ } else {
+ /* immh == 0 would be a failure of the decode logic */
+ g_assert(immh == 1);
unallocated_encoding(s);
return;
}
@@ -7419,20 +7432,14 @@ static void handle_simd_shift_intfp_conv(DisasContext
*s, bool is_scalar,
if (is_scalar) {
elements = 1;
} else {
- elements = is_double ? 2 : is_q ? 4 : 2;
- if (is_double && !is_q) {
- unallocated_encoding(s);
- return;
- }
+ elements = (8 << is_q) >> size;
}
+ fracbits = (16 << size) - immhb;
if (!fp_access_check(s)) {
return;
}
- /* immh == 0 would be a failure of the decode logic */
- g_assert(immh);
-
handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
}
--
2.17.0
- [Qemu-devel] [PULL 09/21] target/arm: Use new min/max expanders, (continued)
- [Qemu-devel] [PULL 09/21] target/arm: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 10/21] target/xtensa: Use new min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 05/21] arm/boot: split load_dtb() from arm_load_kernel(), Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 12/21] tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 04/21] platform-bus-device: use device plug callback instead of machine_done notifier, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 17/21] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 16/21] target/arm: Implement CAS and CASP, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16,
Peter Maydell <=
- [Qemu-devel] [PULL 14/21] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 20/21] target/arm: Fix float16 to/from int16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 19/21] target/arm: Implement vector shifted FCVT for fp16, Peter Maydell, 2018/05/10
- [Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV, Peter Maydell, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/05/10
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/05/14