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Re: [Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext |
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Date: |
Wed, 9 May 2018 08:12:21 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/09/2018 02:39 AM, Michael Clark wrote:
> gen methods should access state from DisasContext. Add misa
> field to the DisasContext struct and remove CPURISCVState
> argument from all gen methods.
>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Cc: Emilio G. Cota <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/translate.c | 74
> ++++++++++++++++++++++++++----------------------
> 1 file changed, 40 insertions(+), 34 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~