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[Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 |
Date: |
Sun, 6 May 2018 11:35:20 +1200 |
The mstatus.MXR alias in sstatus should only be writable
by S-mode if the privileged ISA version >= v1.10. Also MXR
was masked in sstatus CSR read but not sstatus CSR writes.
Now we correctly mask sstatus.mxr in both read and write.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
target/riscv/op_helper.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 101dac1ee8dc..f45ac7306c38 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -234,7 +234,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
target_ulong ms = env->mstatus;
target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
| SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS
- | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ | SSTATUS_SUM | SSTATUS_SD;
+ if (env->priv_ver >= PRIV_VERSION_1_10_0) {
+ mask |= SSTATUS_MXR;
+ }
ms = (ms & ~mask) | (val_to_write & mask);
csr_write_helper(env, ms, CSR_MSTATUS);
break;
@@ -441,7 +444,7 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
case CSR_SSTATUS: {
target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
| SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS
- | SSTATUS_SUM | SSTATUS_SD;
+ | SSTATUS_SUM | SSTATUS_SD;
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
mask |= SSTATUS_MXR;
}
--
2.7.0
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, (continued)
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10,
Michael Clark <=
- [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/05/05
- Re: [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Peter Maydell, 2018/05/08