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[Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_el
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf |
Date: |
Sun, 6 May 2018 11:35:09 +1200 |
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_e.c | 7 +------
hw/riscv/sifive_u.c | 7 +------
hw/riscv/spike.c | 7 +------
hw/riscv/virt.c | 7 +------
4 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 487244890ef8..3e523a073469 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,
size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1bd2bde9b871..adc6c2266275 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,
size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index ae82f4eb6341..cf7f9bcc3950 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,
size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf_ram_sym(kernel_filename, identity_translate, NULL,
+ if (load_elf_ram_sym(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
NULL, true, htif_symbol_callback) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3cc9c8090bfb..c2aa795981d2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,
size_t len)
}
}
-static uint64_t identity_translate(void *opaque, uint64_t addr)
-{
- return addr;
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
- if (load_elf(kernel_filename, identity_translate, NULL,
+ if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
0, ELF_MACHINE, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
--
2.7.0
- [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf,
Michael Clark <=
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05