Re: [Qemu-devel] [PATCH 01/13] target-openrisc: Write back result before FPE exception

[BAndViG]

I've read architecture manual again and found that my actual implementation 
differs from it.

How it should be (my updated view, thanks to your note).
The "Exception Processing" chapters stays than "EPCR (no delay slot)" should 
be "Address of next not executed instruction". And there is nothing about 
write-back discard.  It looks like it makes sense taking into account that 
IEEE-754 typically requires to return specially prepared value if an FPE 
occurs. As I remember correctly there are two approaches to compute the 
returned value. On of them is much simpler than another. For example, for 
overflow the value should be just +(-)Inf for simple approach but specially 
re-scaled for more complex one.

How it is implemented in CAPPUCCINO and MAROCCHINO pipes.
It look like till now I haven't been attentively enough. That's why my 
actual implementation follows "Synchronous/precise" approach that is 
write-back is discarded and "EPCR (no delay slot)" <= "Address of 
instruction that caused exception".

Currently I'm focused on implementation snoop-invalidation logic in 
MAROCCHINO and could not estimate when I could change FPE behavior. However, 
I'm voting to keep QEMU algorithms in consistent with actual HW- 
implementation. I remember that there is at list one QEMU to HW 
inconsistency that is implementation SPR_SR_DX. So Linux could run normally 
only in "SPR_SR_DX emulation" mode on HW SoCs. If we implement FPE 
processing in according to architecture manual now we increase number of 
QEMU-vs-HW inconsistencies.

PS. As I'm not a participant of QEMU developers mailing list, the letter 
could be rejected. Fill free to forward the answer there.

BR
Andrey Bacherov


-----Исходное сообщение----- 
From: Stafford Horne
Sent: Saturday, May 05, 2018 8:19 AM
To: Richard Henderson
Cc: address@hidden ; Richard Henderson ; address@hidden
Subject: Re: [PATCH 01/13] target-openrisc: Write back result before FPE 
exception

On Thu, May 03, 2018 at 10:40:18PM -0700, Richard Henderson wrote:
> From: Richard Henderson <address@hidden>
>
> The architecture manual is unclear about this, but the or1ksim
> does writeback before the exception.  This requires splitting
> the helpers in half, with the exception raised by the second.

I dont really see a problem with this, ccing bandvig who did a lot of the 
fpu
hardware implementation in mor1kx.

> Reviewed-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>

Acked-by: Stafford Horne <address@hidden>

> ---
>  target/openrisc/helper.h     |  25 +++--
>  target/openrisc/fpu_helper.c | 250 
> +++++++++----------------------------------
>  target/openrisc/translate.c  | 101 ++++++++++-------
>  3 files changed, 125 insertions(+), 251 deletions(-)