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[Qemu-devel] [PATCH v1 25/29] target-microblaze: mmu: Remove unused regi
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 25/29] target-microblaze: mmu: Remove unused register state |
Date: |
Thu, 3 May 2018 11:19:18 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Add explicit handling for MMU_R_TLBX and log accesses to
invalid MMU registers. We can now remove the state for
all regs but PID, ZPR and TLBX (0 - 2).
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/mmu.c | 7 +++++--
target/microblaze/mmu.h | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index f4a4c339c9..231803ceea 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
}
r = env->mmu.regs[rn];
break;
+ case MMU_R_TLBX:
+ r = env->mmu.regs[rn];
+ break;
case MMU_R_TLBSX:
qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
break;
default:
- r = env->mmu.regs[rn];
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
break;
}
D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
@@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
break;
}
default:
- env->mmu.regs[rn] = v;
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
break;
}
}
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 113539c6e9..624becfded 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -67,7 +67,7 @@ struct microblaze_mmu
/* We keep a separate ram for the tids to avoid the 48 bit tag width. */
uint8_t tids[TLB_ENTRIES];
/* Control flops. */
- uint32_t regs[8];
+ uint32_t regs[3];
int c_mmu;
int c_mmu_tlb_access;
--
2.14.1
- Re: [Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR, (continued)
- [Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 20/29] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 24/29] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 27/29] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 25/29] target-microblaze: mmu: Remove unused register state,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 28/29] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 26/29] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 29/29] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/03
- Message not available