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[Qemu-devel] [PATCH v1 18/29] target-microblaze: dec_msr: Reuse more cod
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 18/29] target-microblaze: dec_msr: Reuse more code when reg-decoding |
Date: |
Thu, 3 May 2018 11:19:11 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Reuse more code when decoding register numbers.
No functional changes.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 38 +++++++++-----------------------------
1 file changed, 9 insertions(+), 29 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index d2788451fe..05449fb941 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -531,11 +531,9 @@ static void dec_msr(DisasContext *dc)
case 1:
msr_write(dc, cpu_R[dc->ra]);
break;
- case 0x3:
- tcg_gen_mov_i32(cpu_SR[SR_EAR], cpu_R[dc->ra]);
- break;
- case 0x5:
- tcg_gen_mov_i32(cpu_SR[SR_ESR], cpu_R[dc->ra]);
+ case SR_EAR:
+ case SR_ESR:
+ tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
break;
case 0x7:
tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
@@ -562,17 +560,11 @@ static void dec_msr(DisasContext *dc)
case 1:
msr_read(dc, cpu_R[dc->rd]);
break;
- case 0x3:
- tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_EAR]);
- break;
- case 0x5:
- tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_ESR]);
- break;
- case 0x7:
- tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_FSR]);
- break;
- case 0xb:
- tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[SR_BTR]);
+ case SR_EAR:
+ case SR_ESR:
+ case SR_FSR:
+ case SR_BTR:
+ tcg_gen_mov_i32(cpu_R[dc->rd], cpu_SR[sr]);
break;
case 0x800:
tcg_gen_ld_i32(cpu_R[dc->rd],
@@ -582,19 +574,7 @@ static void dec_msr(DisasContext *dc)
tcg_gen_ld_i32(cpu_R[dc->rd],
cpu_env, offsetof(CPUMBState, shr));
break;
- case 0x2000:
- case 0x2001:
- case 0x2002:
- case 0x2003:
- case 0x2004:
- case 0x2005:
- case 0x2006:
- case 0x2007:
- case 0x2008:
- case 0x2009:
- case 0x200a:
- case 0x200b:
- case 0x200c:
+ case 0x2000 ... 0x200c:
rn = sr & 0xf;
tcg_gen_ld_i32(cpu_R[dc->rd],
cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
--
2.14.1
- Re: [Qemu-devel] [PATCH v1 15/29] target-microblaze: Break out trap_userspace(), (continued)
- [Qemu-devel] [PATCH v1 17/29] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 13/29] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 16/29] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 18/29] target-microblaze: dec_msr: Reuse more code when reg-decoding,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 21/29] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 19/29] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 20/29] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/03