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[Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed |
Date: |
Mon, 30 Apr 2018 17:08:35 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Do not clobber the IMM register on reversed load/stores.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ec12fed49d..100883e2cc 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -952,7 +952,6 @@ static void dec_load(DisasContext *dc)
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
tcg_gen_andi_tl(t, t, ~3);
tcg_gen_or_tl(t, t, low);
- tcg_gen_mov_tl(env_imm, t);
tcg_temp_free(low);
break;
}
@@ -1104,7 +1103,6 @@ static void dec_store(DisasContext *dc)
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
tcg_gen_andi_tl(t, t, ~3);
tcg_gen_or_tl(t, t, low);
- tcg_gen_mov_tl(env_imm, t);
tcg_temp_free(low);
break;
}
--
2.14.1
- [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only, Edgar E. Iglesias, 2018/04/30
- [Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only, Edgar E. Iglesias, 2018/04/30
- Re: [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30, Peter Maydell, 2018/04/30