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Re: [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in dis
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly |
Date: |
Thu, 26 Apr 2018 17:05:26 +0000 |
On Wed, Apr 25, 2018 at 4:53 PM Michael Clark <address@hidden> wrote:
> This was added to help debug issues using -d in_asm. It is
> useful to see the instruction bytes, as one can detect if
> one is trying to execute ASCII or device-tree magic.
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> disas/riscv.c | 39 ++++++++++++++++++++-------------------
> 1 file changed, 20 insertions(+), 19 deletions(-)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 74ad16e..2cecf0d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen,
size_t tab, rv_decode *dec)
> char tmp[64];
> const char *fmt;
> - if (dec->op == rv_op_illegal) {
> - size_t len = inst_length(dec->inst);
> - switch (len) {
> - case 2:
> - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst);
> - break;
> - case 4:
> - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst);
> - break;
> - case 6:
> - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst);
> - break;
> - default:
> - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst);
> - break;
> - }
> - return;
> - }
> -
> fmt = opcode_data[dec->op].format;
> while (*fmt) {
> switch (*fmt) {
> @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa,
uint64_t pc, rv_inst inst)
> format_inst(buf, buflen, 16, &dec);
> }
> +#define INST_FMT_2 "%04" PRIx64 " "
> +#define INST_FMT_4 "%08" PRIx64 " "
> +#define INST_FMT_6 "%012" PRIx64 " "
> +#define INST_FMT_8 "%016" PRIx64 " "
> +
> static int
> print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa
isa)
> {
> @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct
disassemble_info *info, rv_isa isa)
> }
> }
> + switch (len) {
> + case 2:
> + (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
> + break;
> + case 4:
> + (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
> + break;
> + case 6:
> + (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
> + break;
> + default:
> + (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
> + break;
> + }
> +
> disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
> (*info->fprintf_func)(info->stream, "%s", buf);
> --
> 2.7.0
- [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 01/35] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly,
Alistair Francis <=
- [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48, Michael Clark, 2018/04/25