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[Qemu-devel] [PULL 08/19] target/arm: Fetch GICv3 state directly from CP
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/19] target/arm: Fetch GICv3 state directly from CPUARMState |
Date: |
Thu, 26 Apr 2018 11:47:04 +0100 |
From: Aaron Lindsay <address@hidden>
This eliminates the need for fetching it from el_change_hook_opaque, and
allows for supporting multiple el_change_hooks without having to hack
something together to find the registered opaque belonging to GICv3.
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 10 ----------
hw/intc/arm_gicv3_cpuif.c | 10 ++--------
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 19a0c03f9b..6bd8ff5917 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2902,16 +2902,6 @@ static inline AddressSpace *arm_addressspace(CPUState
*cs, MemTxAttrs attrs)
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
void *opaque);
-/**
- * arm_get_el_change_hook_opaque:
- * Return the opaque data that will be used by the el_change_hook
- * for this CPU.
- */
-static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
-{
- return cpu->el_change_hook_opaque;
-}
-
/**
* aa32_vfp_dreg:
* Return a pointer to the Dn register within env in 32-bit mode.
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 26f5eeda94..cb9a3a542d 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -29,11 +29,7 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
{
- /* Given the CPU, find the right GICv3CPUState struct.
- * Since we registered the CPU interface with the EL change hook as
- * the opaque pointer, we can just directly get from the CPU to it.
- */
- return arm_get_el_change_hook_opaque(arm_env_get_cpu(env));
+ return env->gicv3state;
}
static bool gicv3_use_ns_bank(CPUARMState *env)
@@ -2615,9 +2611,7 @@ void gicv3_init_cpuif(GICv3State *s)
* it might be with code translated by CPU 0 but run by CPU 1, in
* which case we'd get the wrong value.
* So instead we define the regs with no ri->opaque info, and
- * get back to the GICv3CPUState from the ARMCPU by reading back
- * the opaque pointer from the el_change_hook, which we're going
- * to need to register anyway.
+ * get back to the GICv3CPUState from the CPUARMState.
*/
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
--
2.17.0
- [Qemu-devel] [PULL 04/19] target/arm: Use v7m_stack_read() for reading the frame signature, (continued)
- [Qemu-devel] [PULL 04/19] target/arm: Use v7m_stack_read() for reading the frame signature, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 15/19] hw/arm/highbank: don't make sysram 'nomigrate', Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 02/19] arm: always start from first_cpu when registering loader cpu reset callback, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 01/19] device_tree: Increase FDT_MAX_SIZE to 1 MiB, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 19/19] xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 17/19] hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 05/19] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 16/19] hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate', Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 18/19] timer/aspeed: fix vmstate version id, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 03/19] target/arm: Remove stale TODO comment, Peter Maydell, 2018/04/26
- [Qemu-devel] [PULL 08/19] target/arm: Fetch GICv3 state directly from CPUARMState,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2018/04/26