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[Qemu-devel] [PATCH v12 05/17] hw/arm/smmuv3: Wired IRQ and GERROR helpe
From: |
Eric Auger |
Subject: |
[Qemu-devel] [PATCH v12 05/17] hw/arm/smmuv3: Wired IRQ and GERROR helpers |
Date: |
Wed, 25 Apr 2018 16:15:50 +0200 |
We introduce some helpers to handle wired IRQs and especially
GERROR interrupt. SMMU writes GERROR register on GERROR event
and SW acks GERROR interrupts by setting GERRORn.
The Wired interrupts are edge sensitive hence the pulse usage.
Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
v11 -> v12:
- added Peter's R-b
v9 - v10:
- s/hwaddr/uint64_t in trace-events
- use qemu_log_mask LOG_UNIMP on PRI IRQ
- add a comment saying smmuv3_trigger_irq and smmuv3_write_gerrorn
will become static later on
- write gerrorn without filtering (ie. even if the guest toggles non
active IRQs)
- pulse if at least one new IRQ type
- smmuv3_eventq_irq_enabled and smmuv3_gerror_irq_enabled become
static inline
v7 -> v8:
- remove SMMU_PENDING_GERRORS macro
- properly toggle gerror
- properly sanitize gerrorn write
---
hw/arm/smmuv3-internal.h | 14 +++++++++++
hw/arm/smmuv3.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 3 +++
3 files changed, 81 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 8da38d4..e27c128 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -139,4 +139,18 @@ static inline uint32_t smmuv3_idreg(int regoffset)
return smmuv3_ids[regoffset / 4];
}
+static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
+{
+ return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
+}
+
+static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
+{
+ return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
+}
+
+/* public until callers get introduced */
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index b61f274..c0cedca 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -31,6 +31,70 @@
#include "hw/arm/smmuv3.h"
#include "smmuv3-internal.h"
+/**
+ * smmuv3_trigger_irq - pulse @irq if enabled and update
+ * GERROR register in case of GERROR interrupt
+ *
+ * @irq: irq type
+ * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
+ */
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
+{
+
+ bool pulse = false;
+
+ switch (irq) {
+ case SMMU_IRQ_EVTQ:
+ pulse = smmuv3_eventq_irq_enabled(s);
+ break;
+ case SMMU_IRQ_PRIQ:
+ qemu_log_mask(LOG_UNIMP, "PRI not yet supported\n");
+ break;
+ case SMMU_IRQ_CMD_SYNC:
+ pulse = true;
+ break;
+ case SMMU_IRQ_GERROR:
+ {
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t new_gerrors = ~pending & gerror_mask;
+
+ if (!new_gerrors) {
+ /* only toggle non pending errors */
+ return;
+ }
+ s->gerror ^= new_gerrors;
+ trace_smmuv3_write_gerror(new_gerrors, s->gerror);
+
+ pulse = smmuv3_gerror_irq_enabled(s);
+ break;
+ }
+ }
+ if (pulse) {
+ trace_smmuv3_trigger_irq(irq);
+ qemu_irq_pulse(s->irq[irq]);
+ }
+}
+
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
+{
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t toggled = s->gerrorn ^ new_gerrorn;
+
+ if (toggled & ~pending) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "guest toggles non pending errors = 0x%x\n",
+ toggled & ~pending);
+ }
+
+ /*
+ * We do not raise any error in case guest toggles bits corresponding
+ * to not active IRQs (CONSTRAINED UNPREDICTABLE)
+ */
+ s->gerrorn = new_gerrorn;
+
+ trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
+}
+
static void smmuv3_init_regs(SMMUv3State *s)
{
/**
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 2f3d74a..b77f8d2 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -15,3 +15,6 @@ smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr,
uint64_t pte) "base
#hw/arm/smmuv3.c
smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r)
"addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
+smmuv3_trigger_irq(int irq) "irq=%d"
+smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new
GERROR=0x%x"
+smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new
GERRORN=0x%x"
--
2.5.5
- [Qemu-devel] [PATCH v12 00/17] ARM SMMUv3 Emulation Support, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 02/17] hw/arm/smmu-common: IOMMU memory region and address space setup, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 01/17] hw/arm/smmu-common: smmu base device and datatypes, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 03/17] hw/arm/smmu-common: VMSAv8-64 page table walk, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 05/17] hw/arm/smmuv3: Wired IRQ and GERROR helpers,
Eric Auger <=
- [Qemu-devel] [PATCH v12 04/17] hw/arm/smmuv3: Skeleton, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 06/17] hw/arm/smmuv3: Queue helpers, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 07/17] hw/arm/smmuv3: Implement MMIO write operations, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 08/17] hw/arm/smmuv3: Event queue recording helper, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 10/17] hw/arm/smmuv3: Abort on vfio or vhost case, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 11/17] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 09/17] hw/arm/smmuv3: Implement translate callback, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 12/17] hw/arm/virt: Add SMMUv3 to the virt board, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 14/17] hw/arm/virt: Introduce the iommu option, Eric Auger, 2018/04/25
- [Qemu-devel] [PATCH v12 15/17] hw/arm/smmuv3: Cache/invalidate config data, Eric Auger, 2018/04/25