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[Qemu-devel] [PATCH v6 2/9] i386: Add cache information in X86CPUDefinit
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v6 2/9] i386: Add cache information in X86CPUDefinition |
Date: |
Tue, 10 Apr 2018 19:16:02 -0400 |
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
---
target/i386/cpu.c | 4 ++++
target/i386/cpu.h | 8 ++++++++
2 files changed, 12 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2d3d7d8..8c84fa2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1098,6 +1098,7 @@ struct X86CPUDefinition {
int stepping;
FeatureWordArray features;
const char *model_id;
+ CPUCaches cache_info;
};
static X86CPUDefinition builtin_x86_defs[] = {
@@ -3235,6 +3236,9 @@ static void x86_cpu_load_def(X86CPU *cpu,
X86CPUDefinition *def, Error **errp)
env->features[w] = def->features[w];
}
+ /* Load Cache information from the X86CPUDefinition */
+ memcpy(&env->cache_info, &def->cache_info, sizeof(CPUCaches));
+
/* Special cases not set in the X86CPUDefinition structs: */
/* TODO: in-kernel irqchip for hvf */
if (kvm_enabled()) {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eaed287..aff8396 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1096,6 +1096,13 @@ typedef struct CPUCacheInfo {
} CPUCacheInfo;
+typedef struct CPUCaches {
+ bool valid;
+ CPUCacheInfo l1d_cache;
+ CPUCacheInfo l1i_cache;
+ CPUCacheInfo l2_cache;
+ CPUCacheInfo l3_cache;
+} CPUCaches;
typedef struct CPUX86State {
/* standard registers */
@@ -1282,6 +1289,7 @@ typedef struct CPUX86State {
/* Features that were explicitly enabled/disabled */
FeatureWordArray user_features;
uint32_t cpuid_model[12];
+ CPUCaches cache_info;
/* MTRRs */
uint64_t mtrr_fixed[11];
--
1.8.3.1
- [Qemu-devel] [PATCH v6 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 2/9] i386: Add cache information in X86CPUDefinition,
Babu Moger <=
- [Qemu-devel] [PATCH v6 1/9] i386: Helpers to encode cache information consistently, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 4/9] i386: Add new property to control cache info, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 3/9] i386: Initialize cache information for EPYC family processors, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 5/9] i386: Use the statically loaded cache definitions, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 9/9] i386: Remove generic SMT thread check, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 7/9] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/04/10