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[Qemu-devel] [PATCH v6 19/26] RISC-V: vectored traps are optional
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v6 19/26] RISC-V: vectored traps are optional |
Date: |
Sat, 24 Mar 2018 11:13:34 -0700 |
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f79716a..36b9e8e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -262,11 +262,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
env->sepc = val_to_write;
break;
case CSR_STVEC:
- if (val_to_write & 1) {
- qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not
supported");
- goto do_illegal;
+ /* we do not support vectored traps for asynchrounous interrupts */
+ if ((val_to_write & 3) == 0) {
+ env->stvec = val_to_write >> 2 << 2;
}
- env->stvec = val_to_write >> 2 << 2;
break;
case CSR_SCOUNTEREN:
env->scounteren = val_to_write;
@@ -284,11 +283,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
env->mepc = val_to_write;
break;
case CSR_MTVEC:
- if (val_to_write & 1) {
- qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not
supported");
- goto do_illegal;
+ /* we do not support vectored traps for asynchrounous interrupts */
+ if ((val_to_write & 3) == 0) {
+ env->mtvec = val_to_write >> 2 << 2;
}
- env->mtvec = val_to_write >> 2 << 2;
break;
case CSR_MCOUNTEREN:
env->mcounteren = val_to_write;
--
2.7.0
- [Qemu-devel] [PATCH v6 14/26] RISC-V: Use memory_region_is_ram in pte update, (continued)
[Qemu-devel] [PATCH v6 19/26] RISC-V: vectored traps are optional,
Michael Clark <=
[Qemu-devel] [PATCH v6 10/26] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/24
[Qemu-devel] [PATCH v6 08/26] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/24
[Qemu-devel] [PATCH v6 26/26] RISC-V: Workaround for critical mstatus.FS MTTCG bug, Michael Clark, 2018/03/24
[Qemu-devel] [PATCH v6 20/26] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/24
[Qemu-devel] [PATCH v6 21/26] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/24