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[Qemu-devel] [PATCH v6 24/26] RISC-V: Remove erroneous comment from tran
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v6 24/26] RISC-V: Remove erroneous comment from translate.c |
Date: |
Sat, 24 Mar 2018 11:13:38 -0700 |
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_sar_tl(source1, source1, source2);
break;
- /* fall through to SRA */
#endif
case OPC_RISC_SRA:
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
--
2.7.0
- [Qemu-devel] [PATCH v6 00/26] RISC-V: Fixes and cleanups for QEMU 2.12, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 18/26] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 24/26] RISC-V: Remove erroneous comment from translate.c,
Michael Clark <=
- [Qemu-devel] [PATCH v6 25/26] RISC-V: Fix incorrect disassembly for addiw, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 11/26] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 14/26] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 16/26] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 23/26] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/24
- [Qemu-devel] [PATCH v6 06/26] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/24