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[Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional |
Date: |
Fri, 16 Mar 2018 12:41:17 -0700 |
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f79716a..aa101cc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -262,11 +262,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
env->sepc = val_to_write;
break;
case CSR_STVEC:
- if (val_to_write & 1) {
- qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not
supported");
- goto do_illegal;
+ /* we do not support vectored traps for asynchrounous interrupts */
+ if ((val_to_write & 3) == 0) {
+ env->stvec = val_to_write >> 2 << 2;
}
- env->stvec = val_to_write >> 2 << 2;
break;
case CSR_SCOUNTEREN:
env->scounteren = val_to_write;
@@ -284,11 +283,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
env->mepc = val_to_write;
break;
case CSR_MTVEC:
- if (val_to_write & 1) {
- qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not
supported");
- goto do_illegal;
+ /* we do not support vectored traps for asynchrounous interrupts */
+ if ((val_to_write & 3) == 0) {
+ env->mtvec = val_to_write >> 2 << 2;
}
- env->mtvec = val_to_write >> 2 << 2;
break;
case CSR_MCOUNTEREN:
env->mcounteren = val_to_write;
--
2.7.0
- Re: [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory, (continued)
- [Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional,
Michael Clark <=
- [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup, no-reply, 2018/03/16