Re: [Qemu-devel] [PATCH v2] PowerPC: Add TS bits into msr_mask

[David Gibson]

On Mon, Mar 05, 2018 at 06:53:48PM +0800, address@hidden wrote:
> From: Simon Guo <address@hidden>
> 
> During migration, after MSR bits is synced, cpu_post_load() will use
> msr_mask to determine which PPC MSR bits will be applied into the target
> side. Hardware Transaction Memory(HTM) has been supported since Power8,
> but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM
> from loading TM checkpointed values.
> 
> This patch adds TS bits into msr_mask for Power8, so that transactional
> application can be migrated across qemu.
> 
> Signed-off-by: Simon Guo <address@hidden>

Much better, applied, thanks.

> ---
>  target/ppc/translate_init.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 55c99c9..ca06028 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8689,6 +8689,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>                      (1ull << MSR_DR) |
>                      (1ull << MSR_PMM) |
>                      (1ull << MSR_RI) |
> +                    (1ull << MSR_TS0) |
> +                    (1ull << MSR_TS1) |
>                      (1ull << MSR_LE);
>      pcc->mmu_model = POWERPC_MMU_2_07;
>  #if defined(CONFIG_SOFTMMU)

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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