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[Qemu-devel] [PULL 12/39] target/arm: Add Cortex-M33
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/39] target/arm: Add Cortex-M33 |
Date: |
Fri, 2 Mar 2018 11:06:13 +0000 |
Add a Cortex-M33 definition. The M33 is an M profile CPU
which implements the ARM v8M architecture, including the
M profile Security Extension.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 27d9e90308..e08b1e7943 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1206,6 +1206,35 @@ static void cortex_m4_initfn(Object *obj)
cpu->id_isar5 = 0x00000000;
}
+static void cortex_m33_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd213; /* r0p3 */
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000210;
+ cpu->id_dfr0 = 0x00200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x00101F40;
+ cpu->id_mmfr1 = 0x00000000;
+ cpu->id_mmfr2 = 0x01000000;
+ cpu->id_mmfr3 = 0x00000000;
+ cpu->id_isar0 = 0x01101110;
+ cpu->id_isar1 = 0x02212000;
+ cpu->id_isar2 = 0x20232232;
+ cpu->id_isar3 = 0x01111131;
+ cpu->id_isar4 = 0x01310132;
+ cpu->id_isar5 = 0x00000000;
+ cpu->clidr = 0x00000000;
+ cpu->ctr = 0x8000c000;
+}
+
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
@@ -1697,6 +1726,8 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
--
2.16.2
- [Qemu-devel] [PULL 00/39] target-arm queue, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 03/39] xlnx-zynqmp: Connect the RTC device, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 01/39] xlnx-zynqmp-rtc: Initial commit, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 04/39] decodetree: Propagate return value from translate subroutines, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 02/39] xlnx-zynqmp-rtc: Add basic time support, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 05/39] loader: Add new load_ramdisk_as(), Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 07/39] hw/arm/armv7m: Honour CPU's address space for image loads, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 08/39] target/arm: Define an IDAU interface, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 12/39] target/arm: Add Cortex-M33,
Peter Maydell <=
- [Qemu-devel] [PULL 09/39] armv7m: Forward idau property to CPU object, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 11/39] armv7m: Forward init-svtor property to CPU object, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 15/39] qdev: Add new qdev_init_gpio_in_named_with_opaque(), Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 06/39] hw/arm/boot: Honour CPU's address space for image loads, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 13/39] hw/misc/unimp: Move struct to header file, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property for the reset secure VTOR value, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 17/39] hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 16/39] hw/core/split-irq: Device that splits IRQ lines, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 14/39] include/hw/or-irq.h: Add missing include guard, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 19/39] hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton, Peter Maydell, 2018/03/02