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[Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt num
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions |
Date: |
Thu, 15 Feb 2018 18:36:55 +0000 |
In many of the NVIC registers relating to interrupts, we
have to convert from a byte offset within a register set
into the number of the first interrupt which is affected.
We were getting this wrong for:
* reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>,
NVIC_IABR<n> -- in all these cases we were missing the "* 8"
needed to convert from the byte offset to the interrupt number
(since all these registers use one bit per interrupt)
* writes of NVIC_IPR<n> had the opposite problem of a spurious
"* 8" (since these registers use one byte per interrupt)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ea3b7cce14..c51151fa8a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1724,7 +1724,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
/* fall through */
case 0x180 ... 0x1bf: /* NVIC Clear enable */
val = 0;
- startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
+ startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++)
{
if (s->vectors[startvec + i].enabled &&
@@ -1738,7 +1738,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
/* fall through */
case 0x280 ... 0x2bf: /* NVIC Clear pend */
val = 0;
- startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
+ startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++)
{
if (s->vectors[startvec + i].pending &&
(attrs.secure || s->itns[startvec + i])) {
@@ -1748,7 +1748,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
break;
case 0x300 ... 0x33f: /* NVIC Active */
val = 0;
- startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
+ startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++)
{
if (s->vectors[startvec + i].active &&
@@ -1863,7 +1863,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr
addr,
case 0x300 ... 0x33f: /* NVIC Active */
return MEMTX_OK; /* R/O */
case 0x400 ... 0x5ef: /* NVIC Priority */
- startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
+ startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
if (attrs.secure || s->itns[startvec + i]) {
--
2.16.1
- [Qemu-devel] [PULL 03/20] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers, (continued)
- [Qemu-devel] [PULL 03/20] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 05/20] target/arm: Suppress TB end for FPCR/FPSR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 02/20] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 04/20] target/arm: Enforce FP access to FPCR/FPSR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 01/20] hw/arm/aspeed: directly map the serial device to the system address space, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 06/20] target/arm: Enforce access to ZCR_EL at translation, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 08/20] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 10/20] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 11/20] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 13/20] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions,
Peter Maydell <=
- [Qemu-devel] [PULL 09/20] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 07/20] target/arm: Handle SVE registers when using clear_vec_high, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 12/20] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 14/20] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 16/20] target/arm: Add AIRCR to vmstate struct, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 19/20] bcm2836: Make CPU type configurable, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 20/20] raspi: Raspberry Pi 3 support, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 17/20] target/arm: Migrate v7m.other_sp, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 18/20] target/arm: Implement v8M MSPLIM and PSPLIM registers, Peter Maydell, 2018/02/15
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2018/02/15