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[Qemu-devel] [PULL 06/21] target/arm: Remove ARM_CP_64BIT from ZCR_EL re
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/21] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers |
Date: |
Thu, 15 Feb 2018 13:56:47 +0000 |
From: Richard Henderson <address@hidden>
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 180ab75458..4b102ec356 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4357,7 +4357,7 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo zcr_el1_reginfo = {
.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL1_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4365,7 +4365,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = {
static const ARMCPRegInfo zcr_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL2_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4373,14 +4373,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = {
static const ARMCPRegInfo zcr_no_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_64BIT,
+ .access = PL2_RW,
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
};
static const ARMCPRegInfo zcr_el3_reginfo = {
.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL3_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
.writefn = zcr_write, .raw_writefn = raw_write
};
--
2.16.1
- [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 11/21] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 12/21] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 10/21] target/arm: Handle SVE registers when using clear_vec_high, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 08/21] target/arm: Suppress TB end for FPCR/FPSR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 09/21] target/arm: Enforce access to ZCR_EL at translation, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 05/21] raspi: Add "raspi3" machine type, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 02/21] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 14/21] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 06/21] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers,
Peter Maydell <=
- [Qemu-devel] [PULL 07/21] target/arm: Enforce FP access to FPCR/FPSR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 15/21] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 16/21] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 01/21] hw/arm/aspeed: directly map the serial device to the system address space, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 21/21] target/arm: Implement v8M MSPLIM and PSPLIM registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 17/21] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 04/21] raspi: Raspberry Pi 3 support, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 20/21] target/arm: Migrate v7m.other_sp, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 18/21] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 03/21] bcm2836: Make CPU type configurable, Peter Maydell, 2018/02/15