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[Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register |
Date: |
Tue, 13 Feb 2018 13:00:35 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
As per the Spec v3.00
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
---
hw/sd/sdhci.c | 42 +++++++++++++++++++++---------------------
include/hw/sd/sdhci.h | 2 +-
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 844c5d5..55b3f3a 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -691,7 +691,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr
*dscr)
uint32_t adma1 = 0;
uint64_t adma2 = 0;
hwaddr entry_addr = (hwaddr)s->admasysaddr;
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_ADMA2_32:
dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
sizeof(adma2));
@@ -880,7 +880,7 @@ static void sdhci_data_transfer(void *opaque)
SDHCIState *s = (SDHCIState *)opaque;
if (s->trnmod & SDHC_TRNS_DMA) {
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_SDMA:
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
sdhci_sdma_transfer_single_block(s);
@@ -989,7 +989,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = s->prnsts;
break;
case SDHC_HOSTCTL:
- ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
+ ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
(s->wakcon << 24);
break;
case SDHC_CLKCON:
@@ -1107,7 +1107,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
MASKED_WRITE(s->sdmasysad, mask, value);
/* Writing to last byte of sdmasysad might trigger transfer */
if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt
&&
- s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
+ s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
if (s->trnmod & SDHC_TRNS_MULTI) {
sdhci_sdma_transfer_multi_blocks(s);
} else {
@@ -1159,7 +1159,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
if (!(mask & 0xFF0000)) {
sdhci_blkgap_write(s, value >> 16);
}
- MASKED_WRITE(s->hostctl, mask, value);
+ MASKED_WRITE(s->hostctl1, mask, value);
MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
@@ -1380,7 +1380,7 @@ const VMStateDescription sdhci_vmstate = {
VMSTATE_UINT16(cmdreg, SDHCIState),
VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
VMSTATE_UINT32(prnsts, SDHCIState),
- VMSTATE_UINT8(hostctl, SDHCIState),
+ VMSTATE_UINT8(hostctl1, SDHCIState),
VMSTATE_UINT8(pwrcon, SDHCIState),
VMSTATE_UINT8(blkgap, SDHCIState),
VMSTATE_UINT8(wakcon, SDHCIState),
@@ -1586,7 +1586,7 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset,
unsigned size)
{
SDHCIState *s = SYSBUS_SDHCI(opaque);
uint32_t ret;
- uint16_t hostctl;
+ uint16_t hostctl1;
switch (offset) {
default:
@@ -1598,17 +1598,17 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset,
unsigned size)
* manipulation code see comments in a similar part of
* usdhc_write()
*/
- hostctl = SDHC_DMA_TYPE(s->hostctl) << (8 - 3);
+ hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
- if (s->hostctl & SDHC_CTRL_8BITBUS) {
- hostctl |= ESDHC_CTRL_8BITBUS;
+ if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
+ hostctl1 |= ESDHC_CTRL_8BITBUS;
}
- if (s->hostctl & SDHC_CTRL_4BITBUS) {
- hostctl |= ESDHC_CTRL_4BITBUS;
+ if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
+ hostctl1 |= ESDHC_CTRL_4BITBUS;
}
- ret = hostctl;
+ ret = hostctl1;
ret |= (uint32_t)s->blkgap << 16;
ret |= (uint32_t)s->wakcon << 24;
@@ -1632,7 +1632,7 @@ static void
usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
{
SDHCIState *s = SYSBUS_SDHCI(opaque);
- uint8_t hostctl;
+ uint8_t hostctl1;
uint32_t value = (uint32_t)val;
switch (offset) {
@@ -1695,25 +1695,25 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
/*
* First, save bits 7 6 and 0 since they are identical
*/
- hostctl = value & (SDHC_CTRL_LED |
- SDHC_CTRL_CDTEST_INS |
- SDHC_CTRL_CDTEST_EN);
+ hostctl1 = value & (SDHC_CTRL_LED |
+ SDHC_CTRL_CDTEST_INS |
+ SDHC_CTRL_CDTEST_EN);
/*
* Second, split "Data Transfer Width" from bits 2 and 1 in to
* bits 5 and 1
*/
if (value & ESDHC_CTRL_8BITBUS) {
- hostctl |= SDHC_CTRL_8BITBUS;
+ hostctl1 |= SDHC_CTRL_8BITBUS;
}
if (value & ESDHC_CTRL_4BITBUS) {
- hostctl |= ESDHC_CTRL_4BITBUS;
+ hostctl1 |= ESDHC_CTRL_4BITBUS;
}
/*
* Third, move DMA select from bits 9 and 8 to bits 4 and 3
*/
- hostctl |= SDHC_DMA_TYPE(value >> (8 - 3));
+ hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3));
/*
* Now place the corrected value into low 16-bit of the value
@@ -1724,7 +1724,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
* kernel
*/
value &= ~UINT16_MAX;
- value |= hostctl;
+ value |= hostctl1;
value |= (uint16_t)s->pwrcon << 8;
sdhci_write(opaque, offset, value, size);
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 2a26b46..5459484 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -59,7 +59,7 @@ typedef struct SDHCIState {
uint16_t cmdreg; /* Command Register */
uint32_t rspreg[4]; /* Response Registers 0-3 */
uint32_t prnsts; /* Present State Register */
- uint8_t hostctl; /* Host Control Register */
+ uint8_t hostctl1; /* Host Control Register */
uint8_t pwrcon; /* Power control Register */
uint8_t blkgap; /* Block Gap Control Register */
uint8_t wakcon; /* WakeUp Control Register */
--
1.8.3.1
- [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), (continued)
- [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 36/48] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 12/48] build-sys: remove useless extra*flags variables, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 25/48] sdhci: Fix 64-bit ADMA2, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 34/48] sdhci: implement UHS-I voltage switch, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 33/48] sdbus: add trace events, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register,
Paolo Bonzini <=
- [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 39/48] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 42/48] sdhci: add a check_capab_v3() qtest, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 48/48] travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 47/48] memory: unify loops to sync dirty log bitmap, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 44/48] g364fb: switch to using DirtyBitmapSnapshot, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 41/48] sdhci: check Spec v3 capabilities qtest, Paolo Bonzini, 2018/02/13