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[Qemu-devel] [PATCH v11 29/30] sdhci: add a check_capab_v3() qtest
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v11 29/30] sdhci: add a check_capab_v3() qtest |
Date: |
Thu, 8 Feb 2018 13:48:17 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
---
tests/sdhci-test.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index 70aa0a850e..74a644ceba 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -16,6 +16,8 @@
#define SDHC_CAPAB 0x40
FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); /* since v2 */
FIELD(SDHC_CAPAB, SDMA, 22, 1);
+FIELD(SDHC_CAPAB, SDR, 32, 3); /* since v3 */
+FIELD(SDHC_CAPAB, DRIVER, 36, 3); /* since v3 */
#define SDHC_HCVER 0xFE
static const struct sdhci_t {
@@ -156,6 +158,20 @@ static void check_capab_sdma(QSDHCI *s, uintptr_t addr,
bool supported)
g_assert_cmpuint(capab_sdma, ==, supported);
}
+static void check_capab_v3(QSDHCI *s, uintptr_t addr, uint8_t version)
+{
+ uint64_t capab, capab_v3;
+
+ if (version < 3) {
+ /* before v3 those fields are RESERVED */
+ capab = sdhci_readq(s, addr, SDHC_CAPAB);
+ capab_v3 = FIELD_EX64(capab, SDHC_CAPAB, SDR);
+ g_assert_cmpuint(capab_v3, ==, 0);
+ capab_v3 = FIELD_EX64(capab, SDHC_CAPAB, DRIVER);
+ g_assert_cmpuint(capab_v3, ==, 0);
+ }
+}
+
static QSDHCI *machine_start(const struct sdhci_t *test)
{
QSDHCI *s = g_new0(QSDHCI, 1);
@@ -203,6 +219,7 @@ static void test_machine(const void *data)
check_specs_version(s, test->sdhci.addr, test->sdhci.version);
check_capab_capareg(s, test->sdhci.addr, test->sdhci.capab.reg);
check_capab_readonly(s, test->sdhci.addr);
+ check_capab_v3(s, test->sdhci.addr, test->sdhci.version);
check_capab_sdma(s, test->sdhci.addr, test->sdhci.capab.sdma);
check_capab_baseclock(s, test->sdhci.addr, test->sdhci.baseclock);
--
2.16.1
- [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence), (continued)
- [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 20/30] sdbus: add trace events, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 21/30] sdhci: implement UHS-I voltage switch, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 22/30] sdhci: implement CMD/DAT[] fields in the Present State register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 28/30] sdhci: check Spec v3 capabilities qtest, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 29/30] sdhci: add a check_capab_v3() qtest,
Philippe Mathieu-Daudé <=