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[Qemu-devel] [PATCH 11/54] hw/intc/arm_gicv3: Make reserved register add
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 11/54] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI |
Date: |
Tue, 6 Feb 2018 13:14:32 -0600 |
From: Peter Maydell <address@hidden>
The GICv3 specification says that reserved register addresses
should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR,
because now that we support generating external aborts the
latter will cause an abort on new board models.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
(cherry picked from commit f1945632b43e36bd9f3e0c2feb0e5b152be7ed91)
Signed-off-by: Michael Roth <address@hidden>
---
hw/intc/arm_gicv3_dist.c | 13 +++++++++++++
hw/intc/arm_gicv3_its_common.c | 8 +++-----
hw/intc/arm_gicv3_redist.c | 13 +++++++++++++
3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 3ea3dd0d40..93fe936862 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -817,6 +817,13 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset,
uint64_t *data,
"%s: invalid guest read at offset " TARGET_FMT_plx
"size %u\n", __func__, offset, size);
trace_gicv3_dist_badread(offset, size, attrs.secure);
+ /* The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ r = MEMTX_OK;
+ *data = 0;
} else {
trace_gicv3_dist_read(offset, *data, size, attrs.secure);
}
@@ -852,6 +859,12 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset,
uint64_t data,
"%s: invalid guest write at offset " TARGET_FMT_plx
"size %u\n", __func__, offset, size);
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
+ /* The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ r = MEMTX_OK;
} else {
trace_gicv3_dist_write(offset, data, size, attrs.secure);
}
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index f2cce597a9..48a85524b7 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -67,7 +67,8 @@ static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr
offset,
MemTxAttrs attrs)
{
qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
- return MEMTX_ERROR;
+ *data = 0;
+ return MEMTX_OK;
}
static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
@@ -82,15 +83,12 @@ static MemTxResult gicv3_its_trans_write(void *opaque,
hwaddr offset,
if (ret <= 0) {
qemu_log_mask(LOG_GUEST_ERROR,
"ITS: Error sending MSI: %s\n", strerror(-ret));
- return MEMTX_DECODE_ERROR;
}
-
- return MEMTX_OK;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ITS write at bad offset 0x%"PRIx64"\n", offset);
- return MEMTX_DECODE_ERROR;
}
+ return MEMTX_OK;
}
static const MemoryRegionOps gicv3_its_trans_ops = {
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 77e5cfa327..8a8684d76e 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -455,6 +455,13 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset,
uint64_t *data,
"size %u\n", __func__, offset, size);
trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
size, attrs.secure);
+ /* The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ r = MEMTX_OK;
+ *data = 0;
} else {
trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data,
size, attrs.secure);
@@ -505,6 +512,12 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr
offset, uint64_t data,
"size %u\n", __func__, offset, size);
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
size, attrs.secure);
+ /* The spec requires that reserved registers are RAZ/WI;
+ * so use MEMTX_ERROR returns from leaf functions as a way to
+ * trigger the guest-error logging but don't return it to
+ * the caller, or we'll cause a spurious guest data abort.
+ */
+ r = MEMTX_OK;
} else {
trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data,
size, attrs.secure);
--
2.11.0
- [Qemu-devel] [PATCH 00/54] Patch Round-up for stable 2.11.1, freeze on 2018-02-12, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 09/54] block: Open backing image in force share mode for size probe, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 11/54] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI,
Michael Roth <=
- [Qemu-devel] [PATCH 13/54] virtio_error: don't invoke status callbacks, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 14/54] vhost: remove assertion to prevent crash, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 15/54] hw/sd/pl181: Reset SD card on controller reset, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 19/54] hw/pci-bridge: fix QEMU crash because of pcie-root-port, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 12/54] hw/intc/arm_gic: reserved register addresses are RAZ/WI, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 16/54] hw/sd/milkymist-memcard: Reset SD card on controller reset, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 18/54] scsi-disk: release AioContext in unaligned WRITE SAME case, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 17/54] hw/sd/ssi-sd: Reset SD card on controller reset, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 25/54] i386: Add EPYC-IBPB CPU model, Michael Roth, 2018/02/06
- [Qemu-devel] [PATCH 26/54] linux-user: Fix locking order in fork_start(), Michael Roth, 2018/02/06