Re: [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

[Richard Henderson]

On 02/04/2018 10:22 PM, Michael Clark wrote:
> Add CPU state header, CPU definitions and initialization routines
> 
> Signed-off-by: Michael Clark <address@hidden>
> ---
>  target/riscv/cpu.c      | 385 ++++++++++++++++++++++++++++++++++++++++++++
>  target/riscv/cpu.h      | 256 +++++++++++++++++++++++++++++
>  target/riscv/cpu_bits.h | 417 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 1058 insertions(+)
>  create mode 100644 target/riscv/cpu.c
>  create mode 100644 target/riscv/cpu.h
>  create mode 100644 target/riscv/cpu_bits.h

Reviewed-by: Richard Henderson <address@hidden>

> 
> +static const RISCVCPUInfo riscv_cpus[] = {
> +#ifdef CONFIG_USER_ONLY
> +    { TYPE_RISCV_CPU_ANY,                riscv_any_cpu_init },
> +#else
> +    { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_09, riscv_imafdcsu_priv1_9_cpu_init },
> +    { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_10, riscv_imafdcsu_priv1_10_cpu_init },
> +    { TYPE_RISCV_CPU_IMACU_PRIV_1_10,    riscv_imacu_priv1_10_cpu_init },
> +    { TYPE_RISCV_CPU_IMAC_PRIV_1_10,     riscv_imac_priv1_10_cpu_init },
> +#endif
> +    { NULL, NULL }
> +};

I do wonder if there might be value in providing the more restricted cpus for
CONFIG_USER_ONLY as well.  E.g. toolchain testing, so that you can be sure that
the compiler doesn't emit an instruction that is invalid for a given MISA.


r~