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[Qemu-devel] [PATCH 3/8] hw/intc/armv7m_nvic: Implement M profile cache
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 3/8] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops |
Date: |
Mon, 5 Feb 2018 10:57:15 +0000 |
For M profile cores, cache maintenance operations are done by
writing to special registers in the system register space.
For QEMU, cache operations are always NOPs, since we don't
implement the cache. Implementing these explicitly avoids
a spurious LOG_GUEST_ERROR when the guest uses them.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 06b9598fbe..74b25ce92c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1594,6 +1594,18 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
}
break;
}
+ case 0xf50: /* ICIALLU */
+ case 0xf58: /* ICIMVAU */
+ case 0xf5c: /* DCIMVAC */
+ case 0xf60: /* DCISW */
+ case 0xf64: /* DCCMVAU */
+ case 0xf68: /* DCCMVAC */
+ case 0xf6c: /* DCCSW */
+ case 0xf70: /* DCCIMVAC */
+ case 0xf74: /* DCCISW */
+ case 0xf78: /* BPIALL */
+ /* Cache and branch predictor maintenance: for QEMU these always NOP */
+ break;
default:
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR,
--
2.16.1
- [Qemu-devel] [PATCH 0/8] v8m: minor missing regs and bugfixes, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 7/8] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 6/8] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 5/8] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 8/8] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 3/8] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/8] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 4/8] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 1/8] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC, Peter Maydell, 2018/02/05