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[Qemu-devel] [PULL 16/21] hw/intc/arm_gic: Fix group priority computatio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/21] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs |
Date: |
Thu, 25 Jan 2018 13:43:24 +0000 |
From: Luc MICHEL <address@hidden>
When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is
0, the non-secure BPR value is used. However, this value must be
incremented by one so that it matches the secure world number of
implemented priority bits (NS world has one less priority bit compared
to the Secure world).
Signed-off-by: Luc MICHEL <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: add assert, as the gicv3 code has]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 713de30..b7989d2 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -256,7 +256,8 @@ static int gic_get_group_priority(GICState *s, int cpu, int
irq)
if (gic_has_groups(s) &&
!(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
GIC_TEST_GROUP(irq, (1 << cpu))) {
- bpr = s->abpr[cpu];
+ bpr = s->abpr[cpu] - 1;
+ assert(bpr >= 0);
} else {
bpr = s->bpr[cpu];
}
--
2.7.4
- [Qemu-devel] [PULL 10/21] target/arm: Add ARM_FEATURE_SVE, (continued)
- [Qemu-devel] [PULL 10/21] target/arm: Add ARM_FEATURE_SVE, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 12/21] target/arm: Hoist store to flags output in cpu_get_tb_cpu_state, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 13/21] target/arm: Simplify fp_exception_el for user-only, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 08/21] target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 03/21] target/arm: Mark disas_set_insn_syndrome inline, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 01/21] target/arm: Fix 32-bit address truncation, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 02/21] i.MX: Fix FEC/ENET receive funtions, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 04/21] target/arm: Use pointers in crypto helpers, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 11/21] target/arm: Move cpu_get_tb_cpu_state out of line, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 15/21] hw/intc/arm_gic: Fix C_RPR value on idle priority, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 16/21] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs,
Peter Maydell <=
- [Qemu-devel] [PULL 18/21] hw/arm/virt: Check that the CPU realize method succeeded, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 05/21] target/arm: Use pointers in neon zip/uzp helpers, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 19/21] sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace object, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 21/21] pl110: Implement vertical compare/next base interrupts, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 17/21] hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 14/21] hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending", Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 20/21] xilinx_spips: Correct usage of an uninitialized local variable, Peter Maydell, 2018/01/25
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/01/25
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/01/25