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Re: [Qemu-devel] [PULL 0/4] TCG queued patches
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From: |
Aurelien Jarno |
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Subject: |
Re: [Qemu-devel] [PULL 0/4] TCG queued patches |
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Date: |
Fri, 12 Jan 2018 22:42:54 +0100 |
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User-agent: |
NeoMutt/20170113 (1.7.2) |
On 2018-01-12 13:06, Richard Henderson wrote:
> This includes a fix for the tcg/arm bug exposed by the ppc64 code change
> for comparisons.
>
> It also includes improvements to tcg/arm and tcg/ppc to allow for larger
> CPUFooState structures, as exposed by expanding CPUARMState for 2048-bit
> vector registers.
>
> Note that tcg/mips has the exact same problem. However, the mips isa
> makes it more difficult to fix up. I'd like someone with hardware to
> make this change.
Ok, I'll try to have a look at that.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- [Qemu-devel] [PULL 0/4] TCG queued patches, Richard Henderson, 2018/01/12
- [Qemu-devel] [PULL 1/4] tcg/arm: Fix double-word comparisons, Richard Henderson, 2018/01/12
- [Qemu-devel] [PULL 2/4] tcg/arm: Support tlb offsets larger than 64k, Richard Henderson, 2018/01/12
- [Qemu-devel] [PULL 3/4] tcg/ppc: Support tlb offsets larger than 64k, Richard Henderson, 2018/01/12
- [Qemu-devel] [PULL 4/4] tcg/ppc: Allow a 32-bit offset to the constant pool, Richard Henderson, 2018/01/12
- Re: [Qemu-devel] [PULL 0/4] TCG queued patches,
Aurelien Jarno <=
- Re: [Qemu-devel] [PULL 0/4] TCG queued patches, Peter Maydell, 2018/01/15