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Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition |
Date: |
Thu, 11 Jan 2018 06:32:52 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 |
On 01/10/2018 06:21 PM, Michael Clark wrote:
> Add CPU state header, CPU definitions and initialization routines
>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/cpu.c | 391 +++++++++++++++++++++++++++++++++++++++++++++
> target/riscv/cpu.h | 271 +++++++++++++++++++++++++++++++
> target/riscv/cpu_bits.h | 417
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1079 insertions(+)
> create mode 100644 target/riscv/cpu.c
> create mode 100644 target/riscv/cpu.h
> create mode 100644 target/riscv/cpu_bits.h
Reviewed-by: Richard Henderson <address@hidden>
r~
[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 12/21] RISC-V HART Array, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10