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Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers
From: |
Christoph Hellwig |
Subject: |
Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers |
Date: |
Mon, 8 Jan 2018 15:28:50 +0100 |
User-agent: |
Mutt/1.5.17 (2007-11-01) |
> + if (env->priv_ver >= PRIV_VERSION_1_10_0) {
> + if (get_field(env->satp, SATP_MODE) == VM_1_09_MBARE) {
> + mode = PRV_M;
> + }
> + } else {
> + if (get_field(env->mstatus, MSTATUS_VM) == VM_1_10_MBARE) {
> + mode = PRV_M;
> + }
> + }
This mixes up VM_1_09_MBARE and VM_1_10_MBARE, but they evaluate to
the same value anyway.
And as Richard said just rely on the mmu_idx from cpu_mmu_index. I
actually already did the change to remove it in a patch for a new riscv
CSR I developed and can thus confirm it works fine.
> + case CSR_SPTBR:
This should use CSR_SATP. In fact even if you want to keep 1.9.1 support
I would highly recommend to remove the CSR_SPTBR define and only use
CSR_SATP in code, with sptbr limited to comments to avoid confusion.
- Re: [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition, (continued)
[Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/02
Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers,
Christoph Hellwig <=
[Qemu-devel] [PATCH v1 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/02
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Richard Henderson, 2018/01/03
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/23
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Richard Henderson, 2018/01/23
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/23
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Richard Henderson, 2018/01/24
- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/24
Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/23