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Re: [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array
From: |
Eric Blake |
Subject: |
Re: [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array |
Date: |
Fri, 5 Jan 2018 15:44:31 -0600 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 |
On 01/05/2018 03:41 PM, Antony Pavlov wrote:
> On Wed, 3 Jan 2018 13:44:16 +1300
> Michael Clark <address@hidden> wrote:
>
>> Holds the state of a heterogenous array of RISC-V hardware threads.
>
>
> Hmm, you use SysBusDevice, uint32_t and RISCVCPU types but there is no header
> files
> inclusion to define these types.
>
> I propose this fixup:
>
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -27,6 +27,10 @@
> #ifndef HW_RISCV_HART_H
> #define HW_RISCV_HART_H
>
> +#include "qemu/osdep.h"
NACK to this part. Our policy is that all .c files should include
osdep.h before anything else, and therefore, all .h files can assume
that osdep.h has already been included. Extending that logic, uint32_t
is always available for use in any .h, without having to add any includes.
> +#include "hw/sysbus.h"
> +#include "target/riscv/cpu.h"
But including these headers for SysBusDevice and RISCVCPU makes sense.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
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- Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, (continued)
[Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 12/21] RISC-V HART Array, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/02