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[Qemu-devel] [PATCH v5 10/17] target/m68k: add cpush/cinv
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v5 10/17] target/m68k: add cpush/cinv |
Date: |
Tue, 2 Jan 2018 02:10:25 +0100 |
Add cache lines invalidate and cache lines push
as no-op operations, as we don't have cache.
These instructions are 68040 only.
Signed-off-by: Laurent Vivier <address@hidden>
---
target/m68k/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d463927fcc..2a9a9c8e42 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4558,6 +4558,24 @@ DISAS_INSN(cpushl)
/* Cache push/invalidate. Implement as no-op. */
}
+DISAS_INSN(cpush)
+{
+ if (IS_USER(s)) {
+ gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ return;
+ }
+ /* Cache push/invalidate. Implement as no-op. */
+}
+
+DISAS_INSN(cinv)
+{
+ if (IS_USER(s)) {
+ gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ return;
+ }
+ /* Invalidate cache line. Implement as no-op. */
+}
+
DISAS_INSN(wddata)
{
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
@@ -5736,6 +5754,8 @@ void register_m68k_insns (CPUM68KState *env)
INSN(fsave, f300, ffc0, FPU);
INSN(intouch, f340, ffc0, CF_ISA_A);
INSN(cpushl, f428, ff38, CF_ISA_A);
+ INSN(cpush, f420, ff20, M68040);
+ INSN(cinv, f400, ff20, M68040);
INSN(wddata, fb00, ff00, CF_ISA_A);
INSN(wdebug, fbc0, ffc0, CF_ISA_A);
#endif
--
2.14.3
- [Qemu-devel] [PATCH v5 09/17] target/m68k: softmmu cleanup, (continued)
[Qemu-devel] [PATCH v5 10/17] target/m68k: add cpush/cinv,
Laurent Vivier <=
[Qemu-devel] [PATCH v5 16/17] target/m68k: add the Interrupt Stack Pointer, Laurent Vivier, 2018/01/01
Re: [Qemu-devel] [PATCH v5 00/17] target/m68k: supervisor mode (part 1), no-reply, 2018/01/01