[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 04/11] target/arm: Decode aa64 armv8.1 scalar/vec
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 04/11] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element |
Date: |
Mon, 18 Dec 2017 09:24:18 -0800 |
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++------
1 file changed, 40 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3836e94135..85fc7af491 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11857,12 +11857,23 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
is_long = true;
/* fall through */
case 0xc: /* SQDMULH */
- case 0xd: /* SQRDMULH */
if (u) {
unallocated_encoding(s);
return;
}
break;
+ case 0xd: /* SQRDMULH / SQRDMLAH */
+ if (u && !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
+ case 0xf: /* SQRDMLSH */
+ if (!u || !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
case 0x8: /* MUL */
if (u || is_scalar) {
unallocated_encoding(s);
@@ -12100,13 +12111,36 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
tcg_op, tcg_idx);
}
break;
- case 0xd: /* SQRDMULH */
+ case 0xd: /* SQRDMULH / SQRDMLAH */
+ if (u) { /* SQRDMLAH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
+ if (size == 1) {
+ gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ } else {
+ gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ }
+ } else { /* SQRDMULH */
+ if (size == 1) {
+ gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx);
+ } else {
+ gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx);
+ }
+ }
+ break;
+ case 0xf: /* SQRDMLSH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
if (size == 1) {
- gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
- tcg_op, tcg_idx);
+ gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
} else {
- gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
- tcg_op, tcg_idx);
+ gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
}
break;
default:
--
2.14.3
- [Qemu-devel] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 01/11] target/arm: Add ARM_FEATURE_V8_1_SIMD, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 02/11] target/arm: Decode aa64 armv8.1 scalar three same extra, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 04/11] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 03/11] target/arm: Decode aa64 armv8.1 three same extra, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 05/11] target/arm: Decode aa32 armv8.1 three same, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 08/11] target/arm: Decode aa64 armv8.3 fcadd, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 07/11] target/arm: Add ARM_FEATURE_V8_FCMA, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3 fcmla, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 11/11] target/arm: Decode aa32 armv8.3 2-reg-index, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v2 10/11] target/arm: Decode aa32 armv8.3 3-same, Richard Henderson, 2017/12/18