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[Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() to
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() to not return FSC values |
Date: |
Wed, 13 Dec 2017 18:12:28 +0000 |
Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.
Note that PMSAv5 does not define any guest-visible fault status
register, so the different "fsr" values we were previously
returning are entirely arbitrary. So we can just switch to using
the most appropriae fi->type values without worrying that we
need to special-case FaultInfo->FSC conversion for PMSAv5.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ce9cb6f..b08910b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9544,7 +9544,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env,
uint32_t address,
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, int *prot, uint32_t *fsr)
+ hwaddr *phys_ptr, int *prot,
+ ARMMMUFaultInfo *fi)
{
int n;
uint32_t mask;
@@ -9573,7 +9574,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
}
}
if (n < 0) {
- *fsr = 2;
+ fi->type = ARMFault_Background;
return true;
}
@@ -9585,11 +9586,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
mask = (mask >> (n * 4)) & 0xf;
switch (mask) {
case 0:
- *fsr = 1;
+ fi->type = ARMFault_Permission;
+ fi->level = 1;
return true;
case 1:
if (is_user) {
- *fsr = 1;
+ fi->type = ARMFault_Permission;
+ fi->level = 1;
return true;
}
*prot = PAGE_READ | PAGE_WRITE;
@@ -9605,7 +9608,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
break;
case 5:
if (is_user) {
- *fsr = 1;
+ fi->type = ARMFault_Permission;
+ fi->level = 1;
return true;
}
*prot = PAGE_READ;
@@ -9615,7 +9619,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
break;
default:
/* Bad permission. */
- *fsr = 1;
+ fi->type = ARMFault_Permission;
+ fi->level = 1;
return true;
}
*prot |= PAGE_EXEC;
@@ -9820,7 +9825,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong
address,
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
- phys_ptr, prot, fsr);
+ phys_ptr, prot, fi);
+ *fsr = arm_fi_to_sfsc(fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
--
2.7.4
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI, (continued)
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 13/43] xlnx-zcu102: Add support for the ZynqMP QSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 21/43] target/arm: Split M profile MNegPri mmu index into user and priv, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 22/43] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 25/43] target/arm: Provide fault type enum and FSR conversion functions, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 27/43] target/arm: Convert get_phys_addr_v5() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 23/43] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() to not return FSC values,
Peter Maydell <=
- [Qemu-devel] [PULL 29/43] target/arm: Convert get_phys_addr_lpae() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 28/43] target/arm: Convert get_phys_addr_v6() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 24/43] target/arm: Implement TT instruction, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 31/43] target/arm: Convert get_phys_addr_pmsav7() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 26/43] target/arm: Remove fsr argument from arm_ld*_ptw(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 16/43] linux-headers: update to 4.15-rc1, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 34/43] target/arm: Ignore fsr from get_phys_addr() in do_ats_write(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 32/43] target/arm: Convert get_phys_addr_pmsav8() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode, Peter Maydell, 2017/12/13