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From: | Pierre Morel |
Subject: | Re: [Qemu-devel] [PATCH 6/7] s390x/pci: move the memory region write from pcistg |
Date: | Mon, 13 Nov 2017 10:17:30 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 |
On 10/11/2017 10:51, Cornelia Huck wrote:
On Fri, 10 Nov 2017 17:40:12 +0800 Yi Min Zhao <address@hidden> wrote:在 2017/11/10 上午3:23, Cornelia Huck 写道:On Tue, 7 Nov 2017 18:24:38 +0100 Pierre Morel <address@hidden> wrote:Let's move the memory region write from pcistg into a dedicated function. This allows us to prepare a later patch searching for subregions inside of the memory region.OK, so here is the memory region write. Do we have any sleeping endianness bugs in there for when we wire up tcg? I'm not sure how this plays with the bswaps (see patch 1). But maybe I've just gotten lost somewhere.I think there's no error. For PCI bars' MRs, we got the little-endian data that is exactly fit to the byte ordering of pcilg instruction. For PCI config space, the data has been swapped according to the cpu byte ordering.Host or target cpu?So we use zpci_swap_endian() to swap the data back to the little-endian ordering.
I do not see where we use the zpci_swap_endian() function in this patch or in the zpci_write_bar() function.
That swap is unconditional. If we were running on a little-endian host, it would be wrong, wouldn't it?
I think there is no problem here, we do not use this function but we use the memory_region_dispatch_write() to access a subregion of the PCI device which is defined as DEVICE_LITTLE_ENDIAN
AFAIU The memory access process the endianness correctly.
Signed-off-by: Pierre Morel <address@hidden> Reviewed-by: Yi Min Zhao <address@hidden> --- hw/s390x/s390-pci-inst.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-)
-- Pierre Morel Linux/KVM/QEMU in Böblingen - Germany
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