Re: [Qemu-devel] [PATCH 6/7] s390x/pci: move the memory region write from pcistg

[Yi Min Zhao]

在 2017/11/10 上午3:23, Cornelia Huck 写道:
> On Tue,  7 Nov 2017 18:24:38 +0100
> Pierre Morel <address@hidden> wrote:
>
> > Let's move the memory region write from pcistg into a dedicated
> > function.
> > This allows us to prepare a later patch searching for subregions
> > inside of the memory region.
> OK, so here is the memory region write. Do we have any sleeping
> endianness bugs in there for when we wire up tcg? I'm not sure how this
> plays with the bswaps (see patch 1).
>
> But maybe I've just gotten lost somewhere.
I think there's no error. For PCI bars' MRs, we got the little-endian data
that is exactly fit to the byte ordering of pcilg instruction. For PCI 
config
space, the data has been swapped according to the cpu byte ordering.
So we use zpci_swap_endian() to swap the data back to the little-endian
ordering.
> > Signed-off-by: Pierre Morel <address@hidden>
> > Reviewed-by: Yi Min Zhao <address@hidden>
> > ---
> >   hw/s390x/s390-pci-inst.c | 27 +++++++++++++++++----------
> >   1 file changed, 17 insertions(+), 10 deletions(-)
> >
> > diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
> > index 50135a0..97f62b5 100644
> > --- a/hw/s390x/s390-pci-inst.c
> > +++ b/hw/s390x/s390-pci-inst.c
> > @@ -455,12 +455,27 @@ static int trap_msix(S390PCIBusDevice *pbdev, uint64_t 
> > offset, uint8_t pcias)
> >       }
> >   }
> >   
> > +static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
> > +                                  uint64_t offset, uint64_t data, uint8_t len)
> > +{
> > +    MemoryRegion *mr;
> > +
> > +    if (trap_msix(pbdev, offset, pcias)) {
> > +        offset = offset - pbdev->msix.table_offset;
> > +        mr = &pbdev->pdev->msix_table_mmio;
> > +    } else {
> > +        mr = pbdev->pdev->io_regions[pcias].memory;
> > +    }
> > +
> > +    return memory_region_dispatch_write(mr, offset, data, len,
> > +                                        MEMTXATTRS_UNSPECIFIED);
> > +}
> > +
> >   int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
> >   {
> >       CPUS390XState *env = &cpu->env;
> >       uint64_t offset, data;
> >       S390PCIBusDevice *pbdev;
> > -    MemoryRegion *mr;
> >       MemTxResult result;
> >       uint8_t len;
> >       uint32_t fh;
> > @@ -517,15 +532,7 @@ int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t 
> > r2)
> >               return 0;
> >           }
> >   
> > -        if (trap_msix(pbdev, offset, pcias)) {
> > -            offset = offset - pbdev->msix.table_offset;
> > -            mr = &pbdev->pdev->msix_table_mmio;
> > -        } else {
> > -            mr = pbdev->pdev->io_regions[pcias].memory;
> > -        }
> > -
> > -        result = memory_region_dispatch_write(mr, offset, data, len,
> > -                                     MEMTXATTRS_UNSPECIFIED);
> > +        result = zpci_write_bar(pbdev, pcias, offset, data, len);
> >           if (result != MEMTX_OK) {
> >               program_interrupt(env, PGM_OPERAND, 4);
> >               return 0;