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[Qemu-devel] [PATCH 13/16] target/xtensa: implement salt/saltu
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 13/16] target/xtensa: implement salt/saltu |
Date: |
Fri, 3 Nov 2017 20:45:18 -0700 |
SALT/SALTU are recent additions to the core Xtensa ISA that do
signed/unsigned setcond.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/translate.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f644d9fed22a..da1f712badc7 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2199,6 +2199,16 @@ static void translate_s32e(DisasContext *dc, const
uint32_t arg[],
}
}
+static void translate_salt(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
+ tcg_gen_setcond_i32(par[0],
+ cpu_R[arg[0]],
+ cpu_R[arg[1]], cpu_R[arg[2]]);
+ }
+}
+
static void translate_sext(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
@@ -3667,6 +3677,14 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_ldst,
.par = (const uint32_t[]){MO_UB, false, true},
}, {
+ .name = "salt",
+ .translate = translate_salt,
+ .par = (const uint32_t[]){TCG_COND_LT},
+ }, {
+ .name = "saltu",
+ .translate = translate_salt,
+ .par = (const uint32_t[]){TCG_COND_LTU},
+ }, {
.name = "sext",
.translate = translate_sext,
}, {
--
2.1.4
- [Qemu-devel] [PATCH 00/16] target/xtensa: switch to libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 01/16] target/xtensa: pass actual frame size to the entry helper, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 05/16] target/xtensa: update import_core.sh script for libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 04/16] target/xtensa: extract FPU2000 opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 02/16] target/xtensa: import libisa source, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 03/16] target/xtensa: extract core opcode translators, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 10/16] target/xtensa: tests: fix memctl SR test, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 13/16] target/xtensa: implement salt/saltu,
Max Filippov <=
- [Qemu-devel] [PATCH 09/16] target/xtensa: use libisa for instruction decoding, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 12/16] target/xtensa: add internal/noop SRs and opcodes, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 14/16] target/xtensa: implement GPIO32, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 15/16] target/xtensa: implement const16, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 16/16] target/xtensa: implement disassembler, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 08/16] target/xtensa: switch fsf to libisa, Max Filippov, 2017/11/03
- [Qemu-devel] [PATCH 06/16] target/xtensa: switch dc232b to libisa, Max Filippov, 2017/11/03