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[Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system rese
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset |
Date: |
Tue, 31 Oct 2017 13:11:28 +0000 |
From: Subbaraya Sundeep <address@hidden>
Implemented system reset by creating SYSRESETREQ gpio
out from nvic.
Signed-off-by: Subbaraya Sundeep <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/msf2-soc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 6f97fa9..a8ec2cd 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+static void do_sys_reset(void *opaque, int n, int level)
+{
+ if (level) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
+}
+
static void m2sxxx_soc_initfn(Object *obj)
{
MSF2State *s = MSF2_SOC(obj);
@@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error
**errp)
error_append_hint(errp, "m3clk can not be zero\n");
return;
}
+
+ qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
+ qemu_allocate_irq(&do_sys_reset, NULL, 0));
+
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
for (i = 0; i < MSF2_NUM_UARTS; i++) {
--
2.7.4
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset,
Peter Maydell <=
- [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs, Peter Maydell, 2017/10/31
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2017/10/31