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[Qemu-devel] [PATCH v5 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW
From: |
Francisco Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done |
Date: |
Sun, 29 Oct 2017 11:13:41 +0100 |
Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias <address@hidden>
---
hw/ssi/xilinx_spips.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 7f0f317..159a89d 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
uint8_t addr_length;
if (fifo8_is_empty(&s->tx_fifo)) {
- if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
- s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
- }
xilinx_spips_update_ixr(s);
return;
} else if (s->snoop_state == SNOOP_STRIPING) {
@@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
ret = s->regs[addr] & IXR_ALL;
s->regs[addr] = 0;
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ xilinx_spips_update_ixr(s);
return ret;
case R_INTR_MASK:
mask = IXR_ALL;
--
2.9.3
- Re: [Qemu-devel] [PATCH v5 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands, (continued)
[Qemu-devel] [PATCH v5 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60), Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 04/13] m25p80: Add support for n25q512a11 and n25q512a13, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 06/13] xilinx_spips: Update striping to be big-endian bit order, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 07/13] xilinx_spips: Add support for RX discard and RX drain, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done,
Francisco Iglesias <=
[Qemu-devel] [PATCH v5 09/13] xilinx_spips: Add support for zero pumping, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI, Francisco Iglesias, 2017/10/29
[Qemu-devel] [PATCH v5 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI, Francisco Iglesias, 2017/10/29