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[Qemu-devel] [PATCH v2 10/12] xilinx_spips: Add support for 4 byte addre
From: |
Francisco Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 10/12] xilinx_spips: Add support for 4 byte addresses in the LQSPI |
Date: |
Sat, 21 Oct 2017 23:54:18 +0200 |
Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS.
Signed-off-by: Francisco Iglesias <address@hidden>
---
hw/ssi/xilinx_spips.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index c858a6c..c360af7 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -92,8 +92,9 @@
#define R_LQSPI_CFG_RESET 0x03A002EB
#define LQSPI_CFG_LQ_MODE (1U << 31)
#define LQSPI_CFG_TWO_MEM (1 << 30)
-#define LQSPI_CFG_SEP_BUS (1 << 30)
+#define LQSPI_CFG_SEP_BUS (1 << 29)
#define LQSPI_CFG_U_PAGE (1 << 28)
+#define LQSPI_CFG_ADDR4 (1 << 27)
#define LQSPI_CFG_MODE_EN (1 << 25)
#define LQSPI_CFG_MODE_WIDTH 8
#define LQSPI_CFG_MODE_SHIFT 16
@@ -705,6 +706,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
/* read address */
DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
+ if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
+ fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
+ }
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
--
2.9.3
- [Qemu-devel] [PATCH v2 00/12] Add support for the ZynqMP Generic QSPI, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 02/12] m25p80: Add support for SST READ ID 0x90/0xAB commands, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 03/12] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60), Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 05/12] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 10/12] xilinx_spips: Add support for 4 byte addresses in the LQSPI,
Francisco Iglesias <=
- [Qemu-devel] [PATCH v2 01/12] m25p80: Add support for continuous read out of RDSR and READ_FSR, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 04/12] m25p80: Add support for n25q512a11 and n25q512a13, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 08/12] xilinx_spips: Support configured endiannes of TX/RX registers, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 06/12] xilinx_spips: Update striping to be big-endian bit order, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 12/12] xlnx-zcu102: Add support for the ZynqMP QSPI, Francisco Iglesias, 2017/10/21
- [Qemu-devel] [PATCH v2 11/12] xilinx_spips: Add support for the ZynqMP Generic QSPI, Francisco Iglesias, 2017/10/21